Encoding:

Format:

MULT ac, rs, rt 

Purpose:

Multiply Word

To multiply two 32-bit signed integers, writing the 64-bit result to the specified accumulator.

Description:

 ac = rs31..0 * rt31..0

The right-most 32-bit signed integer value in register rt is multiplied by the corresponding 32-bit signed integer value in register rs, to produce a 64-bit result that is written to the specified accumulator register.

The value of ac selects an accumulator numbered from 0 to 3. When ac=0, this refers to the original HI/LO register pair of the MIPS64 architecture.

In Release 6 of the MIPS Architecture, accumulators are eliminated from MIPS64.

No arithmetic exception occurs under any circumstances.

Restrictions:

On 64-bit processors, if the 32 most-significant bits of register rt or register rs do not contain sign bits (i.e., bits 31 through 63 equal) then the result of the operation is UNPREDICTABLE.

Operation:

if (NotWordValue(GPR[rs]) or NotWordValue(GPR[rt])) then
   UNPREDICTABLE 
endif
temp63..0 = ((GPR[rs]31)32 || GPR[rs]31..0) * ((GPR[rt31)32 || GPR[rt]31..0)
( HI[ac]63..0 || LO[ac]63..0 ) = (temp63)32 || temp63..32 || (temp31)32 || temp31..0

Exceptions:

Reserved Instruction, DSP Disabled

Programming Notes:

In some processors the integer multiply operation may proceed asynchronously and allow other CPU instru ctions to execute before it is complete. An attempt to read LO or HI before the results are written interlocks until the results are ready. Asynchronous execution does not affect the program result, but offers an op portunity for performance improvement by scheduling the multiply so that other instructions can execute in parallel.

Programs that require overflow detection must check for it explicitly.

Where the size of the operands are known, software should place the shorter operand in register rt. This may reduce the latency of the instruction on those processors which implement data-dependent instruction latencies.