|
POOL32A 000000 |
rt |
rs |
ABSQ_S.W 0010000100 |
POOL32Axf 111100 |
|
6 |
5 |
5 |
10 |
6 |
|
SPECIAL3 011111 |
0 |
rt |
rd |
ABSQ_S.W 10001 |
ABSQ_S.PH 010010 |
|
6 |
5 |
5 |
5 |
5 |
6 |
ABSQ_S.W rdt, rts |
microMIPSDSP |
Find Absolute Value of Fractional Word |
Find Absolute Value of Fractional Word
Find the absolute value of a fractional Q31 value with 32-bit saturation.
rdt = sign_extend(sat32(abs(rts31..0)))
The absolute value of the right-most Q31 fractional value in register rts is found, sign-extended to 64 bits, and written to destination register rdt. If the input value is the minimum Q31 value (-1.0 in decimal, 0x80000000 in hexadecimal), the result is saturated to 0x7FFFFFFF before being sign-extended and written to register rdt.
This instruction sets bit 20 in the DSPControl register in the ouflag field if the input value was saturated.
No data-dependent exceptions are possible.
The operands must be values in the specified format. If they are not, the results are UNPREDICTABLE and the values of the operand vectors become UNPREDICTABLE.
temp31..0 = satAbs32( GPR[rts]31..0 )
GPR[rdt]63..0 = (temp31)32 || temp31..0
function satAbs32( a31..0 )
if ( a31..0 = 0x80000000 ) then
DSPControlouflag:20 = 1
temp31..0 = 0x7FFFFFFF
else
if ( a31 = 1 ) then
temp31..0 = -a31..0
else
temp31..0 = a31..0
endif
endif
return temp31..0
endfunction satAbs32
Reserved Instruction, DSP Disabled