Encoding:

Format:

JALRC.HB rt, rs

Purpose:

Jump and Link Register Compact with Hazard Barrier

To execute a procedure call to an instruction address in a register and clear all execution and instruction hazards

Description:

 GPR[rt] = return_addr, PC = GPR[rs], clear execution and instruction hazards

Place the return address link in GPR rt. The return link is the address of the second instruction following the branch, where execution continues after a procedure call.

For processors that do not implement the MIPS64 ISA:

• Jump to the effective target address in GPR rs. Bit 0 of GPR rs is interpreted as the target ISA Mode: if this bit is 0, signal an Address Error exception when the target instruction is fetched because this target ISA Mode is not supported. Otherwise, set bit 0 of the target address to zero, and fetch the instruction.

For processors that do implement the MIPS64 ISA:

• Jump to the effective target address in GPR rs. Set the ISA Mode bit to the value in GPR rs bit 0. Set bit 0 of the target address to zero. If the target ISA Mode bit is 0 and the target address is not 4-byte aligned, an Address

Error exception will occur when the target instruction is fetched.

JALRC.HB implements a software barrier that resolves all execution and instruction hazards created by Coprocessor

0 state changes (for Release 2 implementations, refer to the SYNCI instruction for additional information on resolving instruction hazards created by writing the instruction stream). The effects of this barrier are seen starting with the instruction fetch and decode of the instruction at the PC to which the JALRC.HB instruction jumps. An equivalent barrier is also implemented by the ERET instruction, but that instruction is only available if access to Coprocessor 0 is enabled, whereas JALRC.HB is legal in all operating modes.

This instruction clears both execution and instruction hazards. Refer to the EHB instruction description for the method of clearing execution hazards alone.

Compact jumps do not have delay slots. The instruction after the jump is NOT executed when the jump is executed.

Restrictions:

After modifying an instruction stream mapping or writing to the instruction stream, execution of those instructions has UNPREDICTABLE behavior until the instruction hazard has been cleared with JALRC.HB, JALRSC.HB,

JR.HB, ERET, or DERET. Further, the operation is UNPREDICTABLE if the mapping of the current instruction stream is modified.

Restrictions Related to Multiple Instruction Sets: This instruction can change the active instruction set, if more than

one instruction set is implemented.

If only one instruction set is implemented, then the effective target address must obey the alignment rules of the instruction set. If multiple instruction sets are implemented, the effective target address must obey the alignment rules of the intended instruction set of the target address as specified by the bit 0 or GPR rs.

For processors which implement MIPS and if the ISAMode bit of the target address is MIPS (bit 0 of GPR rs is 0) and address bit 1 is one, an Address Error exception occurs when the jump target is subsequently fetched as an instruction.

For processors that do not implement MIPS ISA, if the intended target ISAMode is MIPS (bit 0 of GPR rs is zero), an

Address Error exception occurs when the jump target is fetched as an instruction.

Any instruction, including a branch or jump, may immediately follow a branch or jump; that is, delay slot restrictions do not apply in Release 6.

Availability and Compatibility:

Release 6 maps JR and JR.HB to JALRC and JALRC.HB with rt = 0:

Release 6 assemblers should accept the JR and JR.HB mnemonics, mapping them to the Release 6 instruction encodings.

Operation:

temp = GPR[rs]
   GPR[rt] = PC + 4
if (Config3ISA = 1) then
      PC  = temp
   else
      PC = tempGPRLEN-1..1 || 0
      ISAMode = temp0
   endif
   ClearHazards()

Exceptions:

None

Programming Notes:

This branch-and-link instruction can select a register for the return link; other link instructions use GPR 31. The default register for GPR rt, if omitted in the assembly language instruction, is GPR 31.

Release 6 JR.HBrs is implemented as JALRC.HB r0,rs. For example, as JALRC.HB with the destination set to the zero register, r0.

This instruction implements the final step in clearing execution and instruction hazards before execution continues. A hazard is created when a Coprocessor 0 or TLB write affects execution or the mapping of the instruction stream, or after a write to the instruction stream. When such a situation exists, software must explicitly indicate to hardware that the hazard should be cleared. Execution hazards alone can be cleared with the EHB instruction. Instruction hazards can only be cleared with a JR.HB, JALRC.HB, or ERET instruction. These instructions cause hardware to clear the hazard before the instruction at the target of the jump is fetched. Note that because these instructions are encoded as jumps, the process of clearing an instruction hazard can often be included as part of a call (JALR) or return (JR) sequence, by simply replacing the original instructions with the HB equivalent.

Example: Clearing hazards due to an ASID change

/*
 * Code used to modify ASID and call a routine with the new
 * mapping established.
 *
 * a0 = New ASID to establish
 * a1 = Address of the routine to call
 */
   mfc0  v0, C0_EntryHi      /* Read current ASID */
   li    v1, ~M_EntryHiASID  /* Get negative mask for field */
   and   v0, v0, v1          /* Clear out current ASID value */
   or    v0, v0, a0          /* OR in new ASID value */
   mtc0  v0, C0_EntryHi      /* Rewrite EntryHi with new ASID */
   jalrc.hb a1               /* Call routine, clearing the hazard */