Encoding:

Format:

CFC1 rt, fs

Purpose:

Move Control Word From Floating Point

To copy a word from an FPU control register to a GPR.

Description:

 GPR[rt] = FP_Control[fs]

Copy the 32-bit word from FP (coprocessor 1) control register fs into GPR rt, sign-extending it to 64 bits.

The definition of this instruction has been extended in Release 5 to support user mode read and write of Status_FR under the control of Config5UFR. This optional feature is meant to facilitate transition from FR=0 to FR=1 floating-point register modes in order to obsolete FR=0 mode in a future architecture release. User code may set and clear Status_FR without kernel intervention, providing kernel explicitly provides permission.

This UFR facility is not supported in Release 6 because Release 6 only allows FR=1 mode. Accessing the UFR and

UNFR registers causes a Reserved Instruction exception in Release 6 because FIR_UFRP is always 0.

The definition of this instruction has been extended in Release 6 to allow user code to read and modify the Config5_FRE bit. Such modification is allowed when this bit is present (as indicated by FIR_UFRP) and user mode

modification of the bit is enabled by the kernel (as indicated by Config5_UFE). Setting Config5_FRE to 1 causes all floating point instructions which are not compatible with FR=1 mode to take an Reserved Instruction exception. This makes it possible to run pre-Release 6 FR=0 floating point code on a Release 6 core which only supports FR=1 mode, provided the kernel has been set up to trap and emulate FR=0 behavior for these instructions. These instructions include floating-point arithmetic instructions that read/write single-precision registers, LWC1, SWC1, MTC1, and

MFC1 instructions.

The FRE facility uses COP1 register aliases FRE and NFRE to access Config5_FRE.

Restrictions:

There are a few control registers defined for the floating point unit. Prior to Release 6, the result is UNPREDICTABLE if fs specifies a register that does not exist. In Release 6 and later, a Reserved Instruction exception occurs if fs specifies a register that does not exist.

The result is UNPREDICTABLE if fs specifies the UNFR or NFRE write-only control. Release 6 and later implementations are required to produce a Reserved Instruction exception; software must assume it is UNPREDICTABLE.

Operation:

   if fs = 0 then
   temp = FIR
elseif fs = 1 then /* read UFR (CP1 Register 1) */
   if FIRUFRP then
      if not Config5UFR then SignalException(ReservedInstruction) endif
      temp = StatusFR
   else
      if ConfigAR >= 2 SignalException(ReservedInstruction) /* Release 6 traps */ 
      endif
      temp = UNPREDICTABLE
   endif
elseif fs = 4 then /* read fs=4 UNFR not supported for reading - UFR suffices */
      if ConfigAR >= 2 SignalException(ReservedInstruction) /* Release 6 traps */ 
      endif
      temp = UNPREDICTABLE
elseif fs=5 then /* user read of FRE, if permitted */
   if ConfigAR <= 2 then temp = UNPREDICTABLE
   else
      if not Config5UFR then SignalException(ReservedInstruction) endif
      temp = 031 || Config5FRE 
   endif
elseif fs = 25 then /* FCCR */
   temp = 024 || FCSR31..25 || FCSR23
elseif fs = 26 then /* FEXR */
   temp = 014 || FCSR17..12 || 05 || FCSR6..2 || 02
elseif fs = 28 then /* FENR */
   temp = 020 || FCSR11.7 || 04 || FCSR24 || FCSR1..0
elseif fs = 31 then /* FCSR */
   temp = FCSR
else
   if Config2AR >= 2 SignalException(ReservedInstruction)
   /*Release 6 traps; includes NFRE*/
   endif
   temp = UNPREDICTABLE
endif
if Config2AR < 2 then
   GPR[rt] = sign_extend(temp)
endif

Exceptions:

Coprocessor Unusable, Reserved Instruction

Historical Information:

For the MIPS I, II and III architectures, the contents of GPR rt are UNPREDICTABLE for the instruction immediately following CFC1.

MIPS V and MIPS32 introduced the three control registers that access portions of FCSR. These registers were not available in MIPS I, II, III, or IV.

MIPS32 Release 5 introduced the UFR and UNFR register aliases that allow user level access to Status_FR. Release 6 removes them.