Encoding:

Format:

MULEQ_S.W.PHL rd, rs, rt

Purpose:

Multiply Vector Fractional Left Halfwords to Expanded Width Products

Multiply two Q15 fractional halfword values to produce a Q31 fractional word result, with saturation.

Description:

rd = sign_extend(sat32(rs31..16 * rt31..16))

The left-most Q15 fractional halfword value from the right-most paired halfword vector in register rs is multiplied by the corresponding Q15 fractional halfword value from register rt. The result is left-shifted one bit position to create a

Q31 format result, sign-extended to 64 bits, and written into the destination register rd. If both input values are -1.0 in

Q15 format (0x8000 in hexadecimal) the result is clamped to the maximum positive Q31 fractional value

(0x7FFFFFFF in hexadecimal) before being sign-extended and written to the destination register.

To stay compliant with the base architecture, this instruction leaves the base HI/LO pair (accumulator ac0) UNPREDICTABLE after the operation completes. The other DSP Module accumulators, ac1, ac2, and ac3 are unmodified.

If the result is saturated, this instruction writes a 1 to bit 21 in the ouflag field of the DSPControl register.

Restrictions:

No data-dependent exceptions are possible.

The operands must be values in the specified format. If they are not, the results are UNPREDICTABLE and the values of the operand vectors become UNPREDICTABLE.

Operation:

temp31..0 = multiplyQ15Q15ouflag21( GPR[rs]31..16, GPR[rt]31..16 )
GPR[rd]63..0 = (temp31)32 || temp31..0
HI[0]63..0 = UNPREDICTABLE
LO[0]63..0 = UNPREDICTABLE
function multiplyQ15Q15ouflag21( a15..0, b15..0 )
   if ( a15..0 = 0x8000 ) and ( b15..0 = 0x8000 ) then
      temp31..0 = 0x7FFFFFFF
      DSPControlouflag:21 = 1
   else
      temp31..0 = ( a15..0 * b15..0 ) << 1
   endif
   return temp31..0
endfunction multiplyQ15Q15ouflag21

Exceptions:

Reserved Instruction, DSP Disabled

Programming Notes:

The base MIPS64 architecture states that after a GPR-targeting multiply instruction such as MUL, the contents of registers HI and LO are UNPREDICTABLE. To maintain compliance with the base architecture this multiply instruction, MULEQ_S.W.PHL, has the same requirement. Software must save and restore the ac0 register if the previous value in the ac0 register is needed following the MULEQ_S.W.PHL instruction.

Note that the requirement on HI and LO does not apply to the new accumulator registers ac1, ac2, and ac3; as a result the values in these accumulators need not be saved.