POOL32S 010110 |
rt |
rs |
0 00 |
sel |
DMTC0 11011 |
POOL32Sxf 111100 |
6 |
5 |
5 |
2 |
3 |
5 |
6 |
DMTGC0 rt, rs, sel |
microMIPS64 |
Doubleword Move to Guest Coprocessor 0 |
Doubleword Move to Guest Coprocessor 0
To move a doubleword from a GPR to a guest context coprocessor 0 register.
CPR[0,rs,sel] = GPR[rt]
The contents of GPR rt are loaded into the guest context coprocessor 0 register specified in the rd and sel fields. Note that not all guest context coprocessor 0 registers support the sel field. In those instances, the sel field must be zero.
The results are UNDEFINED if guest context coprocessor 0 does not contain a register as specified by rs and sel, or if the guest context coprocessor 0 register specified by rd and sel is a 32-bit register or the destination register is the
Guest.Count register.
The guest context does notimplementthe Virtualization Module. Use of this instruction in guest-kernel mode will result in a Reserved Instruction exception, taken in guest mode.
If access to Coprocessor 0 is not enabled, a Coprocessor Unusable Exception is signaled. If access to Coprocessor 0 is enabled but access to 64-bit operations is not enabled, a Reserved Instruction Exception is signaled.
if IsCoprocessorEnabled(0) then if (Config3VZ = 0) then SignalException(ReservedInstruction, 0) break endif if(not Are64bitOperationsEnabled()) then SignalException(ReservedInstruction) endif datadoubleword = GPR[rt] CPR[0,rs,sel] = datadoubleword else SignalException(CoprocessorUnusable, 0) endif
Coprocessor Unusable
Reserved Instruction