Encoding:

Format:

SHRLV.PH rd, rt, rs

Purpose:

Shift Variable Right Logical Pair of Halfwords

To execute a right shift of two independent halfwords in a vector data type by a variable number of bits.

Description:

rd = sign_extend((rt31..16 >> rs3..0) || (rt15..0 >> rs3..0))

The two right-most halfwords in register rt are independently logically shifted right, inserting zeros into the bit positions emptied by the shift. The two halfword results are then written to the corresponding halfword elements in destination register rd.

The shift amount is provided by the four least-significant bits of register rs, which is interpreted as a four bit unsigned integer taking values between 0 and 15. The remaining bits of rs are ignored.

The sign of the left-most halfword result is extended into the 32 most-significant bits of the destination register.

Restrictions:

No data-dependent exceptions are possible.

The operands must be a value in the specified format. If they are not, the results are UNPREDICTABLE and the values of the operand vectors become UNPREDICTABLE.

Operation:

sa3..0 = GPR[rs]3..0
tempB15..0 = 0sa || GPR[rt]31..sa+16 
tempA15..0 = 0sa || GPR[rt]15..sa 
GPR[rd]63..0 = (tempB15)32 || tempB15..0 || tempA15..0 

Exceptions:

Reserved Instruction, DSP Disabled