Encoding:

POOL16D

010011

rd

Immediate

0

6

5

4

1

Format: 

ADDIUS5 rd, decoded_immediate_value

microMIPS

Add Immediate Unsigned Word 5-Bit Register Select (16-bit instr size)

Purpose:

Add Immediate Unsigned Word 5-Bit Register Select (16-bit instr size)

To add a constant to a 32-bit integer

Description: 

GPR[rd] = GPR[rd] + sign_extend(immediate)

The 4-bit immediate field is sign-extended and then added to the 32-bit value in GPR rd. The 32-bit arithmetic result is sign-extended and placed into GPR rd.

The 5-bit register select allows this 16-bit instruction to use any of the 32 GPRs as the destination register.

No Integer Overflow exception occurs under any circumstances.

Table 5-1 Encoded and Decoded Values of Signed Immediate Field

Encoded

Value of

Instr4..1

(Decimal)

Encoded

Value of

Instr4..1

(Hex)

Decoded

Value of

Immediate

(Decimal)

Decoded

Value of

Immediate

(Hex)

0

0x0

0

0x0000

1

0x1

1

0x0001

2

0x2

2

0x0002

3

0x3

3

0x0003

4

0x4

4

0x0004

5

0x5

5

0x0005

6

0x6

6

0x0006

7

0x7

7

0x0007

8

0x8

-8

0xfff8

9

0x9

-7

0xfff9

10

0xa

-6

0xfffa

11

0xb

-5

0xfffb

12

0xc

-4

0xfffc

13

0xd

-3

0xffffd

14

0xe

-2

0xfffe

15

0xf

-1

0xffff

Restrictions:

If GPR rs does not contain a sign-extended 32-bit value (bits 63..31 equal), then the result of the operation is

UNPREDICTABLE.

Operation: 

if NotWordValue(GPR[rs]) then 
   UNPREDICTABLE 
endif
temp = GPR[rd] + sign_extend(immediate)
GPR[rd] = sign_extend(temp31..0)

Exceptions:

None

Programming Notes:

The term "unsigned" in the instruction name is a misnomer; this operation is 32-bit modulo arithmetic that does not trap on overflow. This instruction is appropriate for unsigned arithmetic, such as address arithmetic, or integer arithmetic environments that ignore overflow, such as C language arithmetic.