Encoding:

Format:

TLBINVF 

Purpose:

TLB Invalidate Flush

TLBINVF invalidates a set of TLB entries based on Index match. The virtual address and ASID are ignored in the entry match.

Implementation of the TLBINVF instruction is optional. The implementation of this instruction is indicated by the IE field in Config4.

Support for TLBINVF is recommend for implementations supporting VTLB/FTLB type of MMU.

Implementation of the EntryHI_EHINV field is required for implementation of TLBINV and TLBINVF instructions.

Description:

On execution of the TLBINVF instruction, all entries within range of Index are invalidated.

Behavior of the TLBINVF instruction applies to all applicable TLB entries and is unaffected by the setting of the

Wired register.

• For JTLB-based MMU (Config_MT=1):

TLBINVF causes all entries in the JTLB to be invalidated. Index is unused.

• For VTLB/FTLB-based MMU (Config_MT=4):

If TLB invalidate walk is implemented in your software (Config4_IE=2), then your software must do these steps to flush the entire MMU:

1.one TLBINVF instruction is executed with an index in VTLB range (invalidates all VTLB entries)

2.a TLBINVF instruction is executed for each FTLB set (invalidates all entries in FTLB set)

If TLB invalidate walk is implemented in hardware (Config4_IE=3), then software must do these steps to flush the entire MMU:

1. one TLBINVF instruction is executed (invalidates all entries in both FTLB & VTLB). In this case, Index is unused.

Restrictions:

When Config_MT=4 and Config_IE=2, the operation is UNDEFINED if the contents of the Index register are greater than or equal to the number of available TLB entries.

If access to Coprocessor 0 is not enabled, a Coprocessor Unusable Exception is signaled.

Availability and Compatibility:

Implementation of the TLBINVF instruction is optional. The implementation of this instruction is indicated by the IE field in Config4.

Implementation of EntryHI_EHINV field is required for implementation of TLBINVF instruction.

Pre-Release 6, support for TLBINVF is recommended for implementations supporting VTLB/FTLB type of MMU.

Release 6 (and subsequent releases) support for TLBINV is required for implementations supporting VTLB/FTLB type of MMU.

Release 6: On processors that include a Block Address Translation (BAT) or Fixed Mapping (FM) MMU (Config_MT =

2 or 3), the operation of this instruction causes a Reserved Instruction exception (RI).

Operation:

if ( ConfigMT=1 or (ConfigMT=4 & Config4IE=2 & Index < VTLBsize() )) 
   startnum = 0
   endnum = VTLBsize() - 1
endif
// treating VTLB and FTLB as one array 
if (ConfigMT=4 & Config4IE=2 & Index >= VTLBsize(); ) 
   startnum = start of selected FTLB set // implementation specific
   endnum = end of selected FTLB set - 1 //implementation specifc
endif
if (ConfigMT=4 & Config4IE=3)) 
   startnum = 0
   endnum = TLBsize() + FTLBsize() - 1;
endif
for (i = startnum to endnum) 
   TLB[i]VPN2_invalid = 1
endfor
function VTLBsize 
   SizeExt = ArchRev() >= 6          ?  Config4VTLBSizeExt
         : Config4MMUExtDef == 3     ?  Config4VTLBSizeExt
         : Config4MMUExtDef == 1     ?  Config4MMUSizeExt
         :               0
         ;
    return 1 + ( (SizeExt << 6) | Config1.MMUSize );
endfunction
function FTLBsize 
   if ( Config1MT == 4 ) then
      return ( Config4FTLBWays + 2 ) * ( 1 << C0_Config4FTLBSets );
   else 
      return 0;
   endif
endfunction

Exceptions:

Coprocessor Unusable,