Encoding:

Format:

LLWP rt, rd, (base)

Purpose:

Load Linked Word Paired

To load two words from memory for an atomic read-modify-write, writing a word each to two registers.

Description:

 GPR[rd] = memory[GPR[base]]63..32, GPR[rt] = memory[GPR[base]]31..0

The LLWP and SCWP instructions provide primitives to implement a paired word atomic read-modify-write (RMW) operation at a synchronizable memory location.

The 64-bit paired word, as a concatenation of two words, at the memory location specified by the double-word aligned effective address is read. The least significant word, sign-extended to the GPR register length, is written into

GPR rt,and the most significant word, sign-extended to the GPR register length, is written into GPR rd.

A paired word read or write occurs as a pair of word reads or writes that is double-word atomic.

The instruction has no offset. The effective address is equal to the contents of GPR base.

rd is intentionally positioned in a non-standard bit-range.

The execution of LLWP begins a RMW sequence on the current processor. There can be only one active RMW sequence per processor. When an LLWP is executed it starts an active RMW sequence replacing any other sequence that was active. The RMW sequence is completed by a subsequent SCWP instruction that either completes the RMW sequence atomically and succeeds, or does not and fails.

Successful execution of the LLWP results in setting LLbit and writing CP0 LLAddr, where LLbit is the least-significant bit of LLAddr. LLAddr contains the data-type aligned address of the operation, in this case a double-word.

Executing LLWP on one processor does not cause an action that, by itself, causes a store conditional instruction type for the same block to fail on another processor.

An execution of LLWP does not have to be followed by execution of SCWP; a program is free to abandon the RMW sequence without attempting a write.

Restrictions:

The addressed location must be synchronizable by all processors and I/O devices sharing the location; if it is not, the result is UNPREDICTABLE. Which storage is synchronizable is a function of both CPU and system implementations. See the documentation of the SC instruction for the formal definition.

The architecture optionally allows support for Load-Linked and Store-Conditional instruction types in a cacheless processor. Support for cacheless operation is implementation dependent. In this case, LLAddr is optional.

Providing misaligned support is not a requirement for this instruction.

Availability and Compatibility

This instruction is introduced by Release 6. It is only present if Config5_XNP=0.

Operation:

vAddr = GPR[base]
(pAddr, CCA) = AddressTranslation (vAddr, DATA, LOAD)
// PAIREDWORD: two word data-type that is double-word atomic
memdoubleword = LoadMemory (CCA, PAIREDWORD, pAddr, vAddr, DATA)
GPR[rt] = sign_extend(memdoubleword31..0)
GPR[rd] = sign_extend(memdoubleword63..32)
LLAddr = pAddr // double-word aligned i.e., pAddr2..0 are 0, or not supported.
LLbit = 1

Exceptions:

TLB Refill, TLB Invalid, Reserved Instruction, Address Error, Watch

Programming Notes:

An LLWP instruction for which the two destination registers are the same but non-zero is UNPREDICTABLE. An

LLWP with two zero destination registers followed by a SCWP can be used to accomplish a double-word atomic write.