Encoding:

Format:

TLBGWI

Purpose:

Write Indexed Guest TLB Entry

To write a Guest TLB entry indexed by the Index register, initiated from root mode.

Description:

The Guest TLB entry pointed to by the Guest.Index registerthe Guest.EntryHi, is written from the contents of

Guest.EntryLo0, Guest.EntryLo1, and Guest.PageMask registers. The information written to the Guest TLB

entry may be different from that in the Guest.EntryHi, Guest.EntryLo0, and Guest.EntryLo1 registers, in that:

• The value written to the VPN2 ield of the TLB entry may have those bits set to zero corresponding to the one bits in the Mask ield of the PageMask register (the least signiicant bit of VPN2 corresponds to the least significant bit of the Mask ield). It is implementation dependent whether these bits are preserved or zeroed during a

TLB write.

• The value written to the PFN0 and PFN1 ields of the TLB entry may have those bits set to zero corresponding to the one bits in the Mask ield of PageMask register (the least signiicant bit of PFN corresponds to the least signiicant bit of the Mask ield). It is implementation dependent whether these bits are preserved or zeroed during a

TLB write.

The single G bit in the TLB entry is set from the logical AND of the G bits in the EntryLo0 and EntryLo1 regis-

• ters.

In an implementation supporting GuestID, GuestCtl1_RID is written in the TLB entry.

• If EHINV is implemented, the TLBGWI instruction also acts as an explicit TLB entry invalidate operation. The Guest

TLB entry pointed to by the Guest.Index register is marked invalid when guest EntryHI_EHINV=1.

When EntryHI_EHINV=1, no machine check generating error conditions exist.

Implementation of the TLBGWI invalidate feature is required if the TLBGINV and TLBGINVF instructions are implemented, optional otherwise.

Restrictions:

The operation is UNDEFINED if the contents of the Guest.Index register are greater than or equal to the number of

TLB entries in the guest context.

If access to the root Coprocessor 0 is not enabled, a Coprocessor Unusable Exception is signaled.

On an FTLB enabled system, if Guest.Index is in FTLB range and the page size speciied does not match FTLB page size, recommended behavior is that the write not complete and a Machine Check Exception be signaled.

On an FTLB enabled system, for a write in FTLB range, if the VPN is inconsistent with Index, it is recommended that a Machine Check Exception be signaled.

Itisimplementation dependent whether multiple TLB matches are detected on a TLBGWI,though itisrecommended. If a TLB write detects multiple matches, but not necessarily all multiple matches, then it is recommended that a TLB lookup or TLB probe operation signal a Machine Check Exception on detection of multiple matches.

If multiple match detection is implemented,then on detection,itis recommended thatthe multiple match be invalidated and the write completed. It is recommended that no Machine Check Exception be signaled.

The guest context does notimplementthe Virtualization Module. Use of this instruction in guest-kernel mode will result in a Reserved Instruction Exception, taken in guest mode.

For processors that do not include a TLB in the guest context, the operation of this instruction is UNDEFINED. The preferred implementation is to signal a Reserved Instruction Exception.

Operation:

if IsCoprocessorEnabled(0) then
   if (Config3VZ = 0) then
      SignalException(ReservedInstruction, 0)
      break
   endif
   i = Guest.Index
   if (Config4IE >= 2) then
      Guest.TLB[i]hardware_invalid = 0
      if ( EntryHIEHINV=1 ) then
         Guest.TLB[i]hardware_invalid = 1
      endif
   endif
   Guest.TLB[i]Mask = Guest.PageMaskMask
   Guest.TLB[i]R = Guest.EntryHiR
   Guest.TLB[i]VPN2 = Guest.EntryHiVPN2 and not Guest.PageMaskMask # Impl dependent
   Guest.TLB[i]ASID = Guest.EntryHiASID
   Guest.TLB[i]G = Guest.EntryLo1G and Guest.EntryLo0G
   Guest.TLB[i]PFN1 = Guest.EntryLo1PFN and not Guest.PageMaskMask # Impl dependent
   Guest.TLB[i]C1 = Guest.EntryLo1C
   Guest.TLB[i]D1 = Guest.EntryLo1D
   Guest.TLB[i]V1 = Guest.EntryLo1V
   Guest.TLB[i]PFN0 = Guest.EntryLo0PFN and not Guest.PageMaskMask # Impl dependent
   Guest.TLB[i]C0 = Guest.EntryLo0C
   Guest.TLB[i]D0 = Guest.EntryLo0D
   Guest.TLB[i]V0 = Guest.EntryLo0V
   if (GuestCtl0G1) then
      Guest.TLB[i]GuestID = GuestCtl1RID
   endif
else
   SignalException(CoprocessorUnusable, 0)
endif

Exceptions:

Coprocessor Unusable

Reserved Instruction

Machine Check (disabled if guest EntryHI_EHINV=1.)