POOL32F 010101 |
ft |
fs |
0 |
fmt |
ROUND.L 11001100 |
POOL32FXf 111011 |
6 |
5 |
5 |
1 |
1 |
8 |
6 |
ROUND.L.fmt |
Floating Point Round to Long Fixed Point | |
ROUND.L.S ft, fs |
microMIPS |
Floating Point Round to Long Fixed Point |
ROUND.L.D ft, fs |
microMIPS |
Floating Point Round to Long Fixed Point |
Floating Point Round to Long Fixed Point
To convert an FP value to 64-bit fixed point, rounding to nearest.
FPR[ft] = convert_and_round(FPR[fs])
The value in FPR fs, in format fmt, is converted to a value in 64-bit long fixed point format and rounded to nearest/ even (rounding mode 0). The result is placed in FPR ft.
When the source value is Infinity, NaN, or rounds to an integer outside the range -263 to 263-1, the result cannot be represented correctly and an IEEE Invalid Operation condition exists. The Invalid Operation flag is set in the FCSR.
If the Invalid Operation Enable bit is set in the FCSR, no result is written to ft and an Invalid Operation exception is taken immediately. Otherwise, a default result is written to ft. On cores with FCSRNAN2008=0, the default result is
263-1. On cores with FCSRNAN2008=1, the default result is:
0 when the input value is NaN
263-1 when the input value is +inf or rounds to a number larger than 263-1
-263-1 when the input value is - or rounds to a number smaller than -263-1
The fields fs and ft must specify valid FPRs: fs for type fmt and fd for long fixed point. If the fields are not valid, the result is UNPREDICTABLE.
The operand must be a value in format fmt; if it is not, the result is UNPREDICTABLE and the value of the operand
FPR becomes UNPREDICTABLE.
The result of this instruction is UNPREDICTABLE if the processor is executing in the FR=0 32-bit FPU register model. It is predictable if executing on a 64-bit FPU in the FR=1 mode, but not with FR=0, and not on a 32-bit FPU.
StoreFPR(ft, L, ConvertFmt(ValueFPR(fs, fmt), fmt, L))
Coprocessor Unusable, Reserved Instruction
Inexact, Unimplemented Operation, Invalid Operation