POOL32A 000000 |
rt |
rs |
bp |
BALIGN 00100010 |
POOL32Axf 111100 |
6 |
5 |
5 |
2 |
8 |
6 |
SPECIAL3 011111 |
rs |
rt |
0 |
bp |
BALIGN 10000 |
APPEND 110001 |
6 |
5 |
5 |
3 |
2 |
5 |
6 |
BALIGN rt, rs, bp |
microMIPSDSP-R2 |
Byte Align Contents from Two Registers |
Byte Align Contents from Two Registers
Create a word result by combining a specified number of bytes from each of two source registers.
rt = sign_extend((rt << 8*bp) || (rs >> 8*(4-bp)))
The right-most 32-bit word in register rt is left-shifted as a 32-bit value by bp byte positions, and the right-most word in register rs is right-shifted as a 32-bit value by (4-bp) byte positions. The shifted values are then or-ed together to create a 32-bit result that is sign-extended to 64 bits and written to destination register rt.
The argument bp is provided by the instruction, and is interpreted as an unsigned two-bit integer taking values between zero and three.
No data-dependent exceptions are possible.
if (bp1..0 = 0) or (bp1..0 = 2) then GPR[rt]63..0 = UNPREDICTABLE else temp31..0 = ( GPR[rt]31..0 << (8*bp1..0) ) || ( GPR[rs]31..0 >> (8*(4-bp1..0)) ) GPR[rt]63..0 = (temp31)32 || temp31..0 endif
Reserved Instruction, DSP Disabled