Encoding:

Format:

PRECEQU.PH.QBL rdt, rts

Purpose:

Precision Expand two Unsigned Bytes to Fractional Halfword Values

Expand the precision of two unsigned byte values taken from the two left-most elements of a quad byte vector to create two Q15 fractional halfword values.

Description:

rdt = sign_extend(expand_prec(rts31..24) || expand_prec(rts23..16))

The two left-most unsigned integer byte values from the four right-most byte elements in register rts are expanded to create two Q15 fractional values that are then written to destination register rdt. The precision expansion is achieved by pre-pending a single zero bit (for positive sign) to the original byte value and appending seven least-significant zeros to generate each 16-bit fractional value.

Bit 31 of the result is extended into the 32 most-significant bits of the destination register.

Restrictions:

No data-dependent exceptions are possible.

The operands must be values in the specified format. If they are not, the results are UNPREDICTABLE and the values of the operand vectors become UNPREDICTABLE.

Operation:

tempB15..0 = 01 || GPR[rts]31..24 || 07 
tempA15..0 = 01 || GPR[rts]23..16 || 07 
GPR[rdt]63..0 = (tempB15)32 || tempB15..0 || tempA15..0

Exceptions:

Reserved Instruction, DSP Disabled