Encoding:

POOL32A

000000

rt

rs

rd

0

PRECRQ.PH.W

0011101101

6

5

5

5

1

10

SPECIAL3

011111

rs

rt

rd

PRECRQ.PH.W

10100

CMPU.EQ.QB

010001

6

5

5

5

5

6

Format: 

PRECRQ.PH.W rd, rs, rt

microMIPSDSP

Precision Reduce Fractional Words to Fractional Halfwords

Purpose:

Precision Reduce Fractional Words to Fractional Halfwords

Reduce the precision of two fractional words to produce two fractional halfword values.

Description: 

rd = sign_extend(rt31..16 || rs31..16)

The 16 most-significant bits from each of the right-most Q31 fractional word values in registers rs and rt are written to destination register rd, creating a vector of two Q15 fractional values. The right-most fractional word from the rs register is used to create the left-most Q15 fractional value in rd, and the right-most fractional word from the rt register is used to create the right-most Q15 fractional value.

The sign of the left-most halfword result is sign-extended into the 32 most-significant bits of the destination register.

Restrictions:

No data-dependent exceptions are possible.

The operands must be values in the specified format. If they are not, the results are UNPREDICTABLE and the values of the operand vectors become UNPREDICTABLE.

Operation: 

tempB15..0 = GPR[rs]31..16
tempA15..0 = GPR[rt]31..16
GPR[rd]63..0 = (tempB15)32 || tempB15..0 || tempA15..0

Exceptions:

Reserved Instruction, DSP Disabled