Encoding:

Format:

MFHGC0 rt, rs, sel

Purpose:

Move from High Guest Coprocessor 0

To move the contents of the upper 32-bits of a guest coprocessor 0 register, extended by 32-bits, to a general register.

Description:

 GPR[rt] = Guest.CPR[0,rs,sel][63:32]

The contents ofthe guest coprocessor 0 register speciied by the combination of rs and sel are sign-extended and loaded into general register rt. Note that not all coprocessor 0 registers support the sel ield. In those instances, the sel ield must be zero.

When the coprocessor 0 register speciied is the EntryLo0 or the EntryLo1 register, MFHGC0 must undo the effects of MTHGC0. That is, bits 31:30 of the register must be returned as bits 1:0 of the GPR, and bits 32 and those of greater signiicance must be left shifted by 2 and written to bits 31:2 of the GPR.

This feature supports MIPS32 backward compatability on a MIPS64 system.

Restrictions:

The results are UNDEFINED if guest coprocessor 0 does not contain a register as speciied by rs and sel, or the register exists but is not extended by 32-bits, or the register is extended for XPA, but XPA is not enabled. XPA is a

Release 5 feature.

The guest context does notimplementthe Virtualization Module. Use of this instruction in guest-kernel mode will result in a Reserved Instruction exception, taken in guest mode.

MFHGC0 must behave exactly the same as the corresponding guest MFHC0instruction, exceptthatit will not cause exceptions that are speciic to guest, such as GPSI and GSFC. Speciically, if the guest register is replicated in guest context, then the read will return the register value, if the register is Reserved for Architecture/Implementation or is

Not Available,the read returns 0,if the registeris Shared (e.g., WatchHi, butitis not extended)then the read will always return the register value except that ields invisible to guest are zeroed out.

If access to Coprocessor 0 is not enabled, a Coprocessor Unusable Exception is signaled.

Operation:

PABITS isthe total number of physical address bitsimplemented. The term can be found in the deinition of

EntryLo0 and EntryLo1.

if IsCoprocessorEnabled(0) then
   reg = rs
   data = Guest.CPR[0,reg,sel]
   if (reg,sel = EntryLo1 or reg,sel = EntryLo0) then
      if (Root.Config3LPA = 1 and Root.PageGrainELPA = 1) then // PABITS > 36
         GPR[rt]31:0 = data61..30
         GPR[rt]63..32 = (data61)32 // sign-extend
      endif
   else
      GPR[rt] = sign_extend(data63..32)
   endif
   SignalException(CoprocessorUnusable, 0)
endif

Exceptions:

Coprocessor Unusable

Reserved Instruction