POOL32A 000000 |
rt |
rs |
rd |
0 |
PRECR.QB.PH 0001101101 |
6 |
5 |
5 |
5 |
1 |
10 |
SPECIAL3 011111 |
rs |
rt |
rd |
PRECR.QB.PH 01101 |
CMPU.EQ.QB 010001 |
6 |
5 |
5 |
5 |
5 |
6 |
PRECR.QB.PH rd, rs, rt |
microMIPSDSP-R2 |
Precision Reduce Four Integer Halfwords to Four Bytes |
Precision Reduce Four Integer Halfwords to Four Bytes
Reduce the precision of four integer halfwords to four byte values.
rd = sign_extend(rs23..16 || rs7..0 || rt23..16 || rt7..0)
The 8 least-significant bits from each of the two right-most integer halfword values in registers rs and rt are taken to produce four byte-sized results that are written to the four right-most byte elements in destination register rd. The two bytes values obtained from rs are written to the two left-most destination byte elements, and the two bytes obtained from rt are written to the two right-most destination byte elements.
The sign of the left-most byte result is extended into the 32 most-significant bits of the destination register.
No data-dependent exceptions are possible.
The operands must be a value in the specified format. If they are not, the results are UNPREDICTABLE and the values of the operand vectors become UNPREDICTABLE.
tempD7..0 = GPR[rs]23..16 tempC7..0 = GPR[rs]7..0 tempB7..0 = GPR[rt]23..16 tempA7..0 = GPR[rt]7..0 GPR[rd]63..0 = (tempD7)32 || tempD7..0 || tempC7..0 || tempB7..0 || tempA7..0
Reserved Instruction, DSP Disabled