Encoding:

Format:

SHLL.QB rdt, rts, sa

Purpose:

Shift Left Logical Vector Quad Bytes

Element-wise left shift of four independent bytes in a vector data type by a fixed number of bits.

Description:

rdt = sign_extend((rts31..24 << sa) || (rts23..16 << sa) || (rts15..8 << sa) || (rts7..0 << sa))

The four right-most byte values in register rts are each independently shifted left by sa bits and the sa least significant bits of each value are set to zero. The four independent results are then written to the corresponding byte elements of destination register rdt.

The sign of the left-most byte result is extended into the 32 most-significant bits of the destination register.

This instruction writes a 1 to bit 22 in the DSPControl register in the ouflag field if any of the left shift operations results in an overflow.

Restrictions:

No data-dependent exceptions are possible.

The operands must be values in the specified format. If they are not, the results are UNPREDICTABLE and the values of the operand vectors become UNPREDICTABLE.

Operation:

tempD7..0 = shift8Left( GPR[rts]31..24, sa2..0 )
tempC7..0 = shift8Left( GPR[rts]23..16, sa2..0 )
tempB7..0 = shift8Left( GPR[rts]15..8, sa2..0 )
tempA7..0 = shift8Left( GPR[rts]7..0, sa2..0 )
GPR[rdt]63..0 = (tempD7)32 || tempD7..0 || tempC7..0 || tempB7..0 || tempA7..0
function shift8Left( a7..0, s2..0 )
   if ( s2..0 = 0 ) then
      temp7..0 = a7..0
   else
      sign = a7
      temp7..0 = ( a7-s..0 || 0s )
      discard7..0 = ( sign(8-s) || a6..6-(s-1) )
      if ( discard7..0 != 0x00 ) then
          DSPControlouflag:22 = 1
      endif
   endif
   return temp7..0
endfunction shift8Left

Exceptions:

Reserved Instruction, DSP Disabled