Encoding:

Format:

MULQ_RS.W rd, rs, rt

Purpose:

Multiply Fractional Words to Same Size Product with Saturation and Rounding

Multiply fractional Q31 word values, with saturation and rounding.

Description:

rd = sign_extend(round(sat32(rs31..0 * rt31..0)))

The right-most Q31 fractional format words in registers rs and rt are multiplied together and the product shifted left by one bit position to create a 64-bit fractional format intermediate result. The intermediate result is rounded up by adding a 1 at bit position 31, and then truncated by discarding the 32 least-significant bits to create a 32-bit fractional format result. The result is then sign-extended to 64 bits and written to destination register rd.

If both input multiplicands are equal to -1 (0x80000000 hexadecimal), rounding is not performed and the maximum positive Q31 fractional format value (0x7FFFFFFF hexadecimal) is sign-extended to 64 bits and written to the destination register.

To stay compliant with the base architecture, this instruction leaves the base HI/LO pair (accumulator ac0) UNPREDICTABLE after the operation completes. The other DSP Module accumulators, ac1, ac2, and ac3, are unchanged.

This instruction, on an overflow or underflow of the operation, writes a 1 to bit 21 in the DSPControl register in the

ouflag field.

Restrictions:

No data-dependent exceptions are possible.

The operands must be a value in the specified format. If they are not, the results are UNPREDICTABLE and the values of the operand vectors become UNPREDICTABLE.

Operation:

if ( GPR[rs]31..0 = 0x80000000 ) and ( GPR[rt]31..0 = 0x80000000 ) then
   temp63..0 = 0x7FFFFFFF00000000
   DSPControlouflag:21 = 1
else 
   temp63..0 = ( GPR[rs]31..0 * GPR[rt]31..0 ) << 1
   temp63..0 = temp63..0 + ( 032 || 0x80000000 )
endif
GPR[rd]63..0 = (temp63)32 || temp63..32
HI[0]63..0 = UNPREDICTABLE
LO[0]63..0 = UNPREDICTABLE

Exceptions:

Reserved Instruction, DSP Disabled

Programming Notes:

The base MIPS64 architecture states that after a GPR-targeting multiply instruction such as MUL, the contents of registers HI and LO are UNPREDICTABLE. To maintain compliance with the base architecture, this multiply instruction, MULQ_RS.W, has the same requirement. Software must save and restore the ac0 register if the previous value in the ac0 register is needed following the MULQ_RS.W instruction.

Note that the requirement on HI and LO does not apply to the new accumulator registers ac1, ac2, and ac3; as a result, the values in these accumulators need not be saved.