Encoding:

POOL32A

000000

rt

rs

sa

0

PREPEND

1001010101

6

5

5

5

1

10

SPECIAL3

011111

rs

rt

sa

PREPEND

00001

APPEND

110001

6

5

5

5

5

6

Format: 

PREPEND rt, rs, sa

microMIPSDSP-R2

Right Shift and Prepend Bits to the MSB

Purpose:

Right Shift and Prepend Bits to the MSB

Logically right-shift the first source register, replacing the bits emptied by the shift with bits from the source register.

Description: 

rt = sign_extend(rssa-1..0 || (rt >> sa))

The right-most word value in register rt is logically right-shifted by the specified shift amount sa, and sa bits from the least-significant positions of register rs are written into the sa most-significant bits emptied by the shift. The result is then sign-extended to 64 bits and written to destination register rt.

Restrictions:

No data-dependent exceptions are possible.

The operands must be a value in the specified format. If they are not, the results are UNPREDICTABLE and the values of the operand vectors become UNPREDICTABLE.

Operation: 

if ( sa4..0 = 0 ) then
   temp31..0 = GPR[rt]31..0 
else
   temp31..0 = ( GPR[rs]sa-1..0 || GPR[rt]31..sa )
endif
GPR[rt]63..0 = (temp31)32 || temp31..0

Exceptions:

Reserved Instruction, DSP Disabled