Encoding:

POP60 110000	BLEZALC rt != 00000	00000	offset
POP60 110000	BGEZALC rs = rt != 00000 rt	rs	offset
POP70 111000	BGTZALC rt != 00000	00000	offset
POP70 111000	BLTZALC rs = rt != 00000 rt	rs	offset
POP35 011101	BEQZALC rs < rt rt != 00000	00000	offset
POP37 011111	BNEZALC rs < rt rt != 00000	00000	offset
6	5	5	16

Format:

B{LE,GE,GT,LT,EQ,NE}ZALC		Compact Zero-Compare and Branch-and-Link Instructions
BLEZALC rt, offset	microMIPS32 Release 6	Compact branch-and-link if GPR rt is less than or equal to zero
BGEZALC rt, offset	microMIPS32 Release 6	Compact branch-and-link if GPR rt is greater than or equal to zero
BGTZALC rt, offset	microMIPS32 Release 6	Compact branch-and-link if GPR rt is greater than zero
BLTZALC rt, offset	microMIPS32 Release 6	Compact branch-and-link if GPR rt is less than to zero
BEQZALC rt, offset	microMIPS32 Release 6	Compact branch-and-link if GPR rt is equal to zero
BNEZALC rt, offset	microMIPS32 Release 6	Compact branch-and-link if GPR rt is not equal to zero

Purpose:

Compact Zero-Compare and Branch-and-Link Instructions

BLEZALC: Compact branch-and-link if GPR rt is less than or equal to zero

BGEZALC: Compact branch-and-link if GPR rt is greater than or equal to zero

BGTZALC: Compact branch-and-link if GPR rt is greater than zero

BLTZALC: Compact branch-and-link if GPR rt is less than to zero

BEQZALC: Compact branch-and-link if GPR rt is equal to zero

BNEZALC: Compact branch-and-link if GPR rt is not equal to zero

Description:

if condition(GPR[rt]) then procedure_call branch

The condition is evaluated. If the condition is true, the branch is taken.

Places the return address link in GPR 31. The return link is the address of the instruction immediately following the branch, where execution continues after a procedure call.

The return address link is unconditionally updated.

A 17-bit signed offset (the 16-bit offset field shifted left 1 bits) is added to the address of the instruction following the branch (not the branch itself), to form a PC-relative effective target address.

BLEZALC: the condition is true if and only if GPR rt is less than or equal to zero.

BGEZALC: the condition is true if and only if GPR rt is greater than or equal to zero.

BLTZALC: the condition is true if and only if GPR rt is less than zero.

BGTZALC: the condition is true if and only if GPR rt is greater than zero.

BEQZALC: the condition is true if and only if GPR rt is equal to zero.

BNEZALC: the condition is true if and only if GPR rt is not equal to zero.

Compact branches do not have delay slots. The instruction after a compact branch is only executed if the branch is not taken.

Restrictions:

Any instruction, including a branch or jump, may immediately follow a branch or jump, that is, delay slot restrictions do not apply in Release 6.

Availability and Compatibility:

These instructions are introduced by and required as of Release 6.

Exceptions:

None

Operation:

GPR[31] = PC+4
target_offset = sign_extend( offset || 0¹ )
BLTZALC: cond = GPR[rt] < 0
BLEZALC: cond = GPR[rt] <= 0
BGEZALC: cond = GPR[rt] >= 0
BGTZALC: cond = GPR[rt] > 0
BEQZALC: cond = GPR[rt] = 0
BNEZALC: cond = GPR[rt] != 0
if cond then
  PC = ( PC+4+ sign_extend( target_offset ) )
endif

Programming Notes:

Software that performs incomplete instruction decode may incorrectly decode these new instructions, because of their very tight encoding. For example, a disassembler might look only at the primary opcode field, instruction bits 31-26, to decode BLEZL without checking that the "rt" field is zero. Such software violated the pre-Release 6 architecture specification.

With the 16-bit offset shifted left 2 bits and sign extended, the conditional branch range is ± 128 KBytes. Other instructions such as pre-Release 6 JAL and JALR, or Release 6 JIALC and BALC have larger ranges. In particular,

BALC, with a 26-bit offset shifted by 2 bits, has a 28-bit range, ± 128 MBytes. Code sequences using AUIPC, DAHI,

DATI, and JIALC allow still greater PC-relative range.