Encoding:

Format:

YIELD rs, rt

Purpose:

Conditionally Deschedule or Deallocate the Current Thread

To suspend the current thread of execution, and conditionally deallocate the associated thread context.

Description:

The YIELD instruction takes a single input operand value from a GPR rt. This value is a descriptor of the circumstances under which the issuing thread should be rescheduled.

If GPR rt is zero, the thread is not to be rescheduled at all, and it is instead deallocated and its associated TC storage freed for allocation by a subsequent FORK issued by some other thread.

If GPR rt is negative one (-1), the thread remains eligible for scheduling at the next opportunity, but invokes the processor’s scheduling logic and relinquishes the CPU for any other threads which ought to execute first according to the implemented scheduling policy.

If GPR rt is negative two (-2), the processor’s scheduling logic is not invoked, and the only effect of the instruction is to retrieve the rs value (see below).

All other negative values of the rt register are reserved for future architectural definition by MIPS.

Positive values of rt are treated as a vector of YIELD qualifier (YQ) bits which describe an implementation-dependent set of external or internal core signal conditions under which the YIELDing thread is to be rescheduled. Up to 31 bits of YIELD qualifier state may be supported by a processor, but implementations may provide fewer. To be usable, a

YIELD qualifier bit must be enabled in the YQMask register (see Section 6.8).

If no set bit of rt matches with a set, enabled YQ bit,the TC is blocked until one or more active bits of enabled YQ input match corresponding rt bits. If and when one or more bits match, the TC resumes a running state, and may be rescheduled for execution in accordance with the thread scheduling policy in effect.

The rs output operand specifies a GPR which is to receive a result value. This result contains the bit vector of YQ inputs values enabled by the YQMask register at the time the YIELD completes. Thus, any YQ state that can be waited upon by a YIELD with a positive rt value can also be polled via a YIELD with an rt value of -1 or -2. The value of any rs bits which do not correspond to set bits in the YQMask register is implementation-dependent, typically 0. A zero value of the rs operand field, selecting GPR 0, indicates that no result value is desired.

Restrictions:

If a positive rt value includes a set bit that is not also set in the YQMask register, a Thread exception is raised for the

YIELD instruction, with the EXCPT field of the VPEControl register set to 2 to indicate the Invalid Qualifier case.

If no non-halted dynamically allocatable TC would be activated after a YIELD whose rt value is 0, a Thread exception is raised for the YIELD instruction, with the EXCPT field of the VPEControl register set to 0 to indicate the

Thread Underflow case.

If the processor’s scheduling logic would be invoked as a consequence of an otherwise unexceptional YIELD, one whose rt value is 0 (excluding the Underflow case), -1, or positive (excluding the Invalid Qualifier case), and both the

YSI bit of VPEControl and the DT bit of TCStatus are set, a Thread exception is raised for the YIELD instruction, with

the VPEControl EXCPT field set to 4 to indicate the YIELD Scheduler case.

If multi-threaded operation is unsupported, a Reserved Instruction Exception is raised for the YIELD instruction.

Processor behavior is UNPREDICTABLE if a YIELD instruction is placed in a branch or jump delay slot.

Operation:

if GPR[rt] = 0 then
   ok = 0
   for t in 0...MVPConf0PTC
      if (TC[t].TCBindCurVPE = TCBindCurVPE )
       and (TC[t].TCBindCurTC != TCBindCurTC )
       and (TC[t].TCStatusDA = 1)
       and (TC[t].TCHaltH = 0)
       and (TC[t].TCStatusA = 1) then
         ok = 1
      endif
   endfor
   if ok = 1 then
      TCStatusA = 0
   else
      VPEControlEXCPT = 0
      SignalException(Thread)
   endif
else if GPR[rt] > 0 then
   if (GPR[rt] and (not YQMask)) != 0 then
      VPEControlEXCPT = 2
      SignalException(Thread)
   else
      SetThreadRescheduleCondition(GPR[rt] and YQMask)
   endif
endif
if GPR[rt] != -2 then
   if (VPEControlYSI = 1) and (TCStatusDT = 1) then
      VPEControlEXCPT = 4
      SignalException(Thread)
   else
      ScheduleOtherThreads()
   endif
endif
if rs != 0 then
   GPR[rs] = GetThreadRescheduleCondition()
endif

Exceptions:

Reserved Instruction

Thread