26 |
25 |
21 |
SWC132 100110 |
ft |
base |
offset |
6 |
5 |
5 |
16 |
microMIPS
SWC1 ft, offset(base)
SWC1 ft, offset(base) |
microMIPS |
Store Word from Floating Point |
MFHC0 rt, rs, sel |
microMIPS Release 5 |
Move from High Coprocessor 0 |
Store Word from Floating Point
To store a word from an FPR to memory.
memory[GPR[base] + offset] = FPR[ft]
The low 32-bit word from FPR ft is stored in memory at the location specified by the aligned effective address. The
16-bit signed offset is added to the contents of GPR base to form the effective address.
Pre-Release 6: An Address Error exception occurs if EffectiveAddress1..0 != 0 (not word-aligned).
Release 6 allows hardware to provide address misalignment support in lieu of requiring natural alignment.
Note: The pseudocode is not completely adapted for Release 6 misalignment support as the handling is implementation dependent.
vAddr = sign_extend(offset) + GPR[base] (pAddr, CCA) = AddressTranslation(vAddr, DATA, STORE) pAddr = pAddrPSIZE-1..3 || (pAddr2..0 xor (ReverseEndian || 02)) bytesel = vAddr2..0 xor (BigEndianCPU || 02) datadoubleword = ValueFPR(ft, UNINTERPRETED_WORD) || 08*bytesel StoreMemory(CCA, WORD, datadoubleword, pAddr, vAddr, DATA)
Coprocessor Unusable, Reserved Instruction, TLB Refill, TLB Invalid, TLB Modified, Address Error, Watch