Encoding:

Format:

TLBWR 

Purpose:

Write Random TLB Entry

To write a TLB entry indexed by the Random register, or, in Release 6, write a TLB entry indexed by an implementation-defined location.

Description:

The TLB entry pointed to by the Random register is written from the contents of the EntryHi, EntryLo0, EntryLo1, and PageMask registers. It is implementation dependent whether multiple TLB matches are detected on a TLBWR.

In such an instance, a Machine Check Exception is signaled.

In Release 6, the Random register has been removed. References to Random refer to an implementation-determined value that is not visible to software.

In Release 2 of the Architecture, multiple TLB matches may only be reported on a TLB write. The information written to the TLB entry may be different from that in the EntryHi, EntryLo0, and EntryLo1 registers, in that:

• The value written to the VPN2 field of the TLB entry may have those bits set to zero corresponding to the one bits in the Mask field of the PageMask register (the least significant bit of VPN2 corresponds to the least significant bit of the Mask field). It is implementation dependent whether these bits are preserved or zeroed during a

TLB write.

• The value written to the PFN0 and PFN1 fields of the TLB entry may have those bits set to zero corresponding to the one bits in the Mask field of PageMask register (the least significant bit of PFN corresponds to the least significant bit of the Mask field). It is implementation dependent whether these bits are preserved or zeroed during a

TLB write.

• The single G bit in the TLB entry is set from the logical AND of the G bits in the EntryLo0 and EntryLo1 registers.

Restrictions:

If access to Coprocessor 0 is not enabled, a Coprocessor Unusable Exception is signaled.

Release 6: Processors that include a Block Address Translation (BAT) or Fixed Mapping (FM) MMU (Config_MT = 2 or 3), the operation of this instruction causes a Reserved Instruction exception (RI).

Operation:

i = Random
if (Config4IE >= 1) then 
   TLB[i]VPN2_invalid = 0
   endif
TLB[i]Mask = PageMaskMask
TLB[i]R = EntryHiR
TLB[i]VPN2 = EntryHiVPN2 and not PageMaskMask # Implementation dependent
TLB[i]ASID = EntryHiASID
TLB[i]G = EntryLo1G and EntryLo0G
TLB[i]PFN1 = EntryLo1PFN and not PageMaskMask # Implementation dependent
TLB[i]C1 = EntryLo1C
TLB[i]D1 = EntryLo1D
TLB[i]V1 = EntryLo1V
TLB[i]PFN0 = EntryLo0PFN and not PageMaskMask # Implementation dependent
TLB[i]C0 = EntryLo0C
TLB[i]D0 = EntryLo0D
TLB[i]V0 = EntryLo0V

Exceptions:

Coprocessor Unusable, Machine Check