Encoding:

Format:

JIALC rt, offset

Purpose:

Jump Indexed and Link, Compact

Description:

GPR[31] = PC+4, PC =( GPR[rt] + sign_extend( offset ) )

The jump target is formed by sign extending the offset field of the instruction and adding it to the contents of GPR rt.

The offset is NOT shifted, that is, each bit of the offset is added to the corresponding bit of the GPR.

Places the return address link in GPR 31. The return link is the address of the following instruction, where execution continues after a procedure call returns. Compact jumps do not have delay slots. The instruction after the jump is

NOT executed when the jump is executed.

For processors that do not implement the MIPS64 ISA:

• Jump to the effective target address in GPR rs. Bit 0 of GPR rs is interpreted as the target ISA Mode: if this bit is 0, signal an Address Error exception when the target instruction is fetched because this target ISA Mode is not supported. Otherwise, set bit 0 of the target address to zero, and fetch the instruction.

For processors that do implement the MIPS64 ISA:

• Jump to the effective target address in GPR rs. Set the ISA Mode bit to the value in GPR rs bit 0. Set bit 0 of the target address to zero. If the target ISA Mode bit is 0 and the target address is not 4-byte aligned, an Address

Error exception will occur when the target instruction is fetched.

Compact jumps do not have delay slots. The instruction after the jump is NOT executed when the jump is executed.

Restrictions:

If only one instruction set is implemented, then the effective target address must obey the alignment rules of the instruction set. If multiple instruction sets are implemented, the effective target address must obey the alignment rules of the intended instruction set of the target address as specified by the bit 0 or GPR rs.

For processors that implement MIPS and if the ISAMode bit of the target is MIPS (bit 0 of GPR rs is 0) and address bit 1 is one, an Address Error exception occurs when the jump target is subsequently fetched as an instruction.

For processors that do not implement MIPS ISA, if the intended target ISAMode is MIPS (bit 0 of GPR rs is zero), an

Address Error exception occurs when the jump target is fetched as an instruction.

Any instruction, including a branch or jump, may immediately follow a branch or jump, that is, delay slot restrictions do not apply in Release 6.

Availability and Compatibility:

This instruction is introduced by and required as of Release 6.

Exceptions:

None

Operation:

temp = GPR[rt] + sign_extend(offset)
GPR[31] = PC + 4
if (Config3ISA = 1) then
      PC = temp 
   else
      PC = (tempGPRLEN-1..1 || 0)
      ISAMode = temp0
   endif

Programming Notes:

JIALC does NOT shift the offset before adding it the register. This can be used to eliminate tags in the least significant bits that would otherwise produce misalignment. It also allows JIALC to be used as a substitute for the JALX instruction, removed in Release 6, where the lower bits of the target PC, formed by the addition of GPR[rt] and the unshifted offset, specify the target ISAmode.