Encoding:

Format:

JRCADDIUSP decoded_immediate

Purpose:

Jump Register Compact, Adjust Stack Pointer (16-bit)

To execute a branch to an instruction address in a register and adjust stack pointer

Description:

PC = GPR[ra]; SP = SP + zero_extend(Immediate << 2)

For processors that do not implement the MIPS64 ISA:

• Jump to the effective target address in GPR rs. Bit 0 of GPR rs is interpreted as the target ISA Mode: if this bit is 0, signal an Address Error exception when the target instruction is fetched because this target ISA Mode is not supported. Otherwise, set bit 0 of the target address to zero, and fetch the instruction.

For processors that do implement the MIPS64 ISA:

• Jump to the effective target address in GPR rs. Set the ISA Mode bit to the value in GPR rs bit 0. Set bit 0 of the target address to zero. If the target ISA Mode bit is 0 and the target address is not 4-byte aligned, an Address

Error exception will occur when the target instruction is fetched.

The 5-bit immediate field is first shifted left by two bits and then zero-extended. This amount is then added to the 32bit value of GPR 29 and the 32-bit arithmetic result is sign-extended and placed into GPR 29. No Integer Overflow exception occurs under any circumstances for the update of GPR 29.

It is implementation-specific whether interrupts are disabled during the sequence of operations generated by this instruction.

Compact jumps do not have delay slots. The instruction after the jump is NOT executed when the jump is executed.

Restrictions:

If only one instruction set is implemented, then the effective target address must obey the alignment rules of the instruction set. If multiple instruction sets are implemented, the effective target address must obey the alignment rules of the intended instruction set of the target address as specified by the bit 0 or GPR rs.

For processors which implement MIPS64 and the ISAMode bit of the target address is MIPS64 (bit 0 of GPR rs is 0) and address bit 1 is one, an Address Error exception occurs when the jump target is subsequently fetched as an instruction.

For processors that do not implement MIPS64 ISA, if the intended target ISAMode is MIPS64 (bit 0 of GPR rs is zero), an Address Error exception occurs when the jump target is fetched as an instruction.

If GPR 29 does not contain a sign-extended 32-bit value (bits 63..31 equal), then the result of the operation is

UNPREDICTABLE.

Any instruction, including a branch or jump, may immediately follow a branch or jump, that is, delay slot restrictions do not apply in Release 6.

Operation:

   PC = GPR[31]GPRLEN-1..1 || 0
   if ( Config3ISA > 1 )
      ISAMode = GPR[31]0
   endif
   if NotWordValue(GPR[29]) then 
      UNPREDICTABLE 
   endif
   temp = GPR[29] + zero_extend(immediate || 02) 
   GPR[29] = sign_extend(temp31..0)

Exceptions:

None.

Programming Notes: