Encoding:

Format:

SEH rt, rs

Purpose:

Sign-Extend Halfword

To sign-extend the least significant halfword of GPR rs and store the value into GPR rt.

Description:

 GPR[rt] = SignExtend(GPR[rs]15..0)

The least significant halfword from GPR rs is sign-extended and stored in GPR rt.

Restrictions:

In implementations prior to Release 2 of the architecture, this instruction resulted in a Reserved Instruction exception.

If GPR rs does not contain a sign-extended 32-bit value (bits 63..31 equal), then the result of the operation is

UNPREDICTABLE.

Operation:

if NotWordValue(GPR[rs]) then
   UNPREDICTABLE
endif
GPR[rt] = sign_extend(GPR[rs]15..0)

Exceptions:

Reserved Instruction

Programming Notes:

The SEH instruction can be used to convert two contiguous halfwords to sign-extended word values in three instructions. For example:

lw    t0, 0(a1)           /* Read two contiguous halfwords */
seh   t1, t0              /* t1 = lower halfword sign-extended to word */
sra   t0, t0, 16          /* t0 = upper halfword sign-extended to word */

Zero-extended halfwords can be created by changing the SEH and SRA instructions to ANDI and SRL instructions, respectively.

For symmetry with the SEB and SEH instructions, you expect that there would be ZEB and ZEH instructions that zero-extend the source operand and expect that the SEW and ZEW instructions would exist to sign- or zero-extend a word to a doubleword. These instructions do not exist because there are functionally-equivalent instructions already in the instruction set. The following table shows the instructions providing the equivalent functions.

Expected InstructionFunctionEquivalent Instruction

Zero-Extend Byte

            ZEB rx,ry                          ANDI rx,ry,0xFF 

Zero-Extend Halfword

            ZEH rx,ry                         ANDI rx,ry,0xFFFF

Sign-Extend Word

            SEW rx,ry                            SLL rx,ry,0
           ZEW rx,rx1Zero-Extend Word

                                             DINSP32 rx,r0,32,32

1. The equivalent instruction uses rx for both source and destination, so the expected instruction is limited to one register