Encoding:

Format:

LWC2 rt, offset(base)

Purpose:

Load Word to Coprocessor 2

To load a word from memory to a COP2 register.

Description:

 CPR[2,rt,0] = memory[GPR[base] + offset]

The contents of the 32-bit word at the memory location specified by the aligned effective address are fetched and placed into the low word of COP2 (Coprocessor 2) general register rt. The signed offset is added to the contents of

GPR base to form the effective address.

Restrictions:

Pre-Release 6: An Address Error exception occurs if +EffectiveAddress_1..0 != 0 (not word-aligned).

Release 6 allows hardware to provide address misalignment support in lieu of requiring natural alignment.

Note: The pseudocode is not completely adapted for Release 6 misalignment support as the handling is implementation dependent.

Availability and Compatibility

This instruction has been recoded for Release 6.

Operation:

vAddr = sign_extend(offset) + GPR[base]
(pAddr, CCA) = AddressTranslation (vAddr, DATA, LOAD)
pAddr = pAddrPSIZE-1..3 || (pAddr2..0 xor (ReverseEndian || 02))
memdoubleword = LoadMemory(CCA, DOUBLEWORD, pAddr, vAddr, DATA)
bytesel = vAddr2..0 xor (BigEndianCPU || 02)
CPR[2,rt,0] = sign_extend(memdoubleword31+8*bytesel..8*bytesel)

Exceptions:

TLB Refill, TLB Invalid, Address Error, Reserved Instruction, Coprocessor Unusable, Watch

Programming Notes:

Release 6 implements an 11-bit offset, whereas all release levels lower than Release 6 implement a 16-bit offset.