Encoding:

Format:

MULSA.W.PH ac, rs, rt

Purpose:

Multiply and Subtract Vector Integer Halfword Elements and Accumulate

To multiply and s ubtract two integer vector elements using full-size intermediate products, accumulating the result into the specified accumulator.

Description:

ac = ac + ((rs31..16 * rt31..16) - (rs15..0 * rt15..0))

Each of the two right-most halfword integer elements from register rt are multiplied by the corresponding elements in

rs to create two word results. The right-most result is subtracted from the left-most result to generate the intermediate

result, which is then added to the specified 64-bit accumulator.

The value of ac selects an accumulator numbered from 0 to 3. When ac=0, this refers to the original HI/LO register pair of the MIPS64 architecture.

This instruction does not set any bits of the ouflag field in the DSPControl register.

Restrictions:

No data-dependent exceptions are possible.

The operands must be a value in the specified format. If they are not, the result is UNPREDICTABLE and the values of the operand vectors become UNPREDICTABLE.

Operation:

tempB31..0 = (GPR[rs]31..16 * GPR[rt]31..16)
tempA31..0 = (GPR[rs]15..0 * GPR[rt]15..0)
dotp32..0 = ( (tempB31) || tempB31..0 ) - ( (tempA31) || tempA31..0 )
acc63..0 = ( HI[ac]31..0 || LO[ac]31..0 ) + ( (dotp32)31 || dotp32..0 )
( HI[ac]63..0 || LO[ac]63..0 ) = (acc63)32 || acc63..32 || (acc31)32 || acc31..0

Exceptions:

Reserved Instruction, DSP Disabled