Encoding:

Format:

TLBGWR

Purpose:

Write Random Guest TLB Entry

To write a Guest TLB entry indexed by the Random register, initiated from root mode.

Description:

The Guest TLB entry pointed to by the Guest.Random register is written from the contents of the Guest.EntryHi,

Guest.EntryLo0, Guest.EntryLo1, and Guest.PageMask registers.

The information written to the Guest TLB entry may be different from that in the Guest.EntryHi, Guest.EntryLo0, and Guest.EntryLo1 registers, in that:

• The value written to the VPN2 ield of the Guest TLB entry may have those bits set to zero corresponding to the one bits in the Mask ield of the Guest.PageMask register (the least signiicant bit of VPN2 corresponds to the least signiicant bit of the Mask ield). It is implementation dependent whether these bits are preserved or zeroed during a Guest TLB write.

• The value written to the PFN0 and PFN1 ields of the TLB entry may have those bits set to zero corresponding to the one bits in the Mask ield of Guest.PageMask register (the least signiicant bit of PFN corresponds to the least signiicant bit of the Mask ield). It is implementation dependent whether these bits are preserved or zeroed during a Guest TLB write.

The single G bit in the Guest TLB entry is set from the logical AND of the G bits in the Guest.EntryLo0 and

• Guest.EntryLo1 registers.

In an implementation supporting GuestID, GuestCtl1_RID is written in the TLB entry.

• Restrictions:

If access to Coprocessor 0 is not enabled, a Coprocessor Unusable Exception is signaled.

On an VTLB/FTLB enabled implementation, if the Pagemask register contains a page size differing from the FTLB page size deined in Conig4, then the write goes into a random entry in the VTLB.

Itis implementation dependent whether multiple TLB matches are detected on a TLBGWR,though itis recommended. If a TLB write detects multiple matches, but not necessarily all multiple matches, then a TLB lookup or TLB probe operation should signal a Machine Check Exception on detection of multiple matches.

If multiple match detection is implemented, then on detection, the multiple match should be invalidated and the write completed. No Machine Check Exception should be signaled.

The guest context does notimplementthe Virtualization Module. Use of this instruction in guest-kernel mode will result in a Reserved Instruction exception, taken in guest mode.

For processors that do not include a TLB in the guest context, the operation of this instruction is UNDEFINED. The preferred implementation is to signal a Reserved Instruction Exception.

Operation:

if IsCoprocessorEnabled(0) then
      SignalException(ReservedInstruction, 0)
      break
   endif
   i = Guest.Random
   if (Config4IE >= 2) then
      Guest.TLB[i]hardware_invalid = 0
      if ( EntryHIEHINV=1 ) then
         Guest.TLB[i]hardware_invalid = 1
      endif
   endif
   Guest.TLB[i]Mask = Guest.PageMaskMask
   Guest.TLB[i]R = Guest.EntryHiR
   Guest.TLB[i]VPN2 = Guest.EntryHiVPN2 and not Guest.PageMaskMask # Impl. dependent
   Guest.TLB[i]ASID = Guest.EntryHiASID
   Guest.TLB[i]G = Guest.EntryLo1G and Guest.EntryLo0G
   Guest.TLB[i]PFN1 = Guest.EntryLo1PFN and not PageMaskMask # Impl. dependent
   Guest.TLB[i]C1 = Guest.EntryLo1C
   Guest.TLB[i]D1 = Guest.EntryLo1D
   Guest.TLB[i]V1 = Guest.EntryLo1V
   Guest.TLB[i]PFN0 = Guest.EntryLo0PFN and not PageMaskMask # Impl. dependent
   Guest.TLB[i]C0 = Guest.EntryLo0C
   Guest.TLB[i]D0 = Guest.EntryLo0D
   Guest.TLB[i]V0 = Guest.EntryLo0V
   if (GuestCtl0G1) then
      Guest.TLB[i]GuestID = GuestCtl1RID
   endif
else
   SignalException(CoprocessorUnusable, 0)
endif

Exceptions:

Coprocessor Unusable

Reserved Instruction

Machine Check (implementation dependent)