Encoding:

Format:

LHU16 rt, left_shifted_offset(base)

Purpose:

Load Halfword Unsigned (16-bit instr size)

To load a halfword from memory as an unsigned value

Description:

 GPR[rt] = memory[GPR[base] + (offset <= 2)]

The contents of the 16-bit halfword at the memory location specified by the aligned effective address are fetched, zero-extended, and placed in GPR rt. The 4-bit unsigned offset is left shifted by one bit and then added to the contents of GPR base to form the effective address.

Restrictions:

The 3-bit register fields can only specify GPRs $2-$7, $16, $17.

Pre-Release 6: The effective address must be naturally-aligned. If the least-significant bit of the address is non-zero, an Address Error exception occurs.

Release 6 allows hardware to provide address misalignment support in lieu of requiring natural alignment.

Note: The pseudocode is not completely adapted for Release 6 misalignment support as the handling is implementation dependent.

Operation:

vAddr = zero_extend(offset || 0) + GPR[base]
(pAddr, CCA) = AddressTranslation (vAddr, DATA, LOAD)
pAddr = pAddrPSIZE-1..3 || (pAddr2..0 xor (ReverseEndian2 || 0))
memdoubleword = LoadMemory (CCA, HALFWORD, pAddr, vAddr, DATA)
byte = vAddr2..0 xor (BigEndianCPU2 || 0)
GPR[rt] = zero_extend(memdoubleword15+8*byte..8*byte)

Exceptions:

TLB Refill, TLB Invalid, Address Error, Watch