Encoding:

Format:

SHLLV_S.W rd, rt, rs

Purpose:

Shift Left Logical Variable Vector Word

A left shift of the right-most word in a vector data type by a variable number of bits, with optional saturation.

Description:

rd = sign_extend(sat32(rt31..0 << rs4..0))

The right-most word element in register rt is shifted left by shift bits, inserting zeros into the least-significant bit positions emptied by the shift. If the shift results in an overflow the intermediate result is saturated to either the maximum positive or the minimum negative 32-bit value, depending on the sign of the original unshifted value.

The shifted result is then sign-extended to 64 bits and written to destination register rd.

The five least-significant bits of rs are used as the shift value, interpreted as a five-bit unsigned integer; the remaining bits of rs are ignored.

This instruction writes a 1 to bit 22 in the DSPControl register in the ouflag field if either of the left shift op erations results in an overflow or saturation.

Restrictions:

No data-dependent exceptions are possible.

The operands must be values in the specified format. If they are not, the results are UNPREDICTABLE and the values of the operand vectors become UNPREDICTABLE.

Operation:

temp31..0 = sat32ShiftLeft( GPR[rt]31..0, GPR[rs]4..0 )
GPR[rd]63..0 = (temp31)32 || temp31..0

Exceptions:

Reserved Instruction, DSP Disabled