POOL32S 010110 |
rt |
rs |
0 00 |
sel |
DMTC0 01011 |
POOL32Sxf 111100 |
6 |
5 |
5 |
2 |
3 |
5 |
6 |
DMTC0 rt, rs |
microMIPS64 |
Doubleword Move to Coprocessor 0 |
DMTC0 rt, rs, sel |
microMIPS64 |
Doubleword Move to Coprocessor 0 |
Doubleword Move to Coprocessor 0
To move a doubleword from a GPR to a coprocessor 0 register.
CPR[0,rs,sel] = GPR[rt]
The contents of GPR rt are loaded into the coprocessor 0 register specified in the rd and sel fields. Not all coprocessor
0 registers support the sel field. In those instances, the sel field must be zero.
The results are UNDEFINED if coprocessor 0 does not contain a register as specified by rs and sel, or if the coprocessor 0 register specified by rd and sel is a 32-bit register.
// 'Width' returns width (32/64) of data returned by CPR. if ((Width(CPR[0,rs,sel]) = 32) and (ConfigAR>=2) ) then dataword <- GPR[rt]31:0 CPR[0,rs,sel] <- dataword elseif ((Width(CPR[0,rs,sel]) = 32) and (ConfigAR<2)) then UNDEFINED else datadoubleword <- GPR[rt] CPR[0,rs,sel] <- datadoubleword endif
Coprocessor Unusable, Reserved Instruction