Encoding:

POOL32A

000000

rt

rs

sa

SHRL.PH

001111

POOL32Axf

111100

6

5

5

4

6

6

SPECIAL3

011111

0

sa

rt

rd

SHRL.PH

11001

SHLL.QB

010011

6

1

4

5

5

5

6

Format: 

SHRL.PH rdt, rts, sa

microMIPSDSP-R2

Shift Right Logical Two Halfwords

Purpose:

Shift Right Logical Two Halfwords

To execute a right shift of two independent halfwords in a vector data type by a fixed number of bits.

Description: 

rdt = sign_extend((rts31..16 >> sa) || (rts15..0 >> sa))

The two right-most halfwords in register rts are independently logically shifted right, inserting zeros into the bit positions emptied by the shift. The two halfword results are then written to the corresponding halfword elements in destination register rdt.

The shift amount is provided by the sa field, which is interpreted as a four bit unsigned integer taking values between

0 and 15.

The sign of the left-most halfword result is extended into the 32 most-significant bits of the destination register.

Restrictions:

No data-dependent exceptions are possible.

The operands must be a value in the specified format. If they are not, the results are UNPREDICTABLE and the values of the operand vectors become UNPREDICTABLE.

Operation: 

tempB15..0 = 0sa || GPR[rts]31..sa+16 
tempA15..0 = 0sa || GPR[rts]15..sa 
GPR[rdt]63..0 = (tempB15)32 || tempB15..0 || tempA15..0

Exceptions:

Reserved Instruction, DSP Disabled