Encoding:

Format:

MTHGC0 rt, rs, sel

Purpose:

Move to High Guest Coprocessor 0

To move the contents of a general register to the upper 32-bits of a guest coprocessor 0 register that has been extended by 32-bits.

Description:

 Guest.CPR[0, rs, sel][63:32] = GPR[rt]

The contents of general register rt are loaded into the guest coprocessor 0 register speciied by the combination of rs and sel. Not all coprocessor 0 registers support the the sel ield. In those instances, the sel ield must be set to zero.

When the guest coprocessor 0 destination register speciied is the EntryLo0 or the EntryLo1 register, bits 1:0 of the

GPR appear at bits 31:30 of EntryLo0 or the EntryLo1 ields. This is to compensate for RI/XI which were shifted to bits 63:62 by MTC0 of EntryLo0 or the EntryLo1.

If RI/XI are not supported,then the shift must still occur, but

MFHC0 willreturn 0s forthese two ields. The GPR is right shifted by 2 to vacate the lower 2-bits, and 2 0s are is written to the upper 32-bits MIPS64 EntryLo0 or EntryLo1, excluding RI/XI shifted in from the left. The result that were placed in bits 63:62 i.e., the write must appear atomic as if both MTC0 and MTHC0 occured together.

This feature supports MIPS32 backward compatability on a MIPS64 system.

Restrictions:

The results are UNDEFINED if guest coprocessor 0 does not contain a register as speciied by rs and sel, or if the register exists but is not extended by 32-bits, or the register is extended for XPA, but XPA is not enabled. XPA is a

Release 5 feature.

MTHGC0 must behave exactly the same as the corresponding guest MTHC0instruction, exceptthatit will not cause exceptions that are speciic to guest, such as GPSI and GSFC. Speciically, if the guest register is replicated in guest context, then the write must complete, if the register is Reserved for Architecture/Implementation or is Not Available, the write is ignored, if the register is Shared (such as WatchHi) then the write always completes but does not effect ields invisible to guest.

In a 64-bit processor, the MTHC0 instruction writes only the lower 32 bits of register rt into the upper 32-bits of the guest coprocessor register speciied by rd and sel if that register is extended by MIPS32 Release 5. Speciically, the only registers extended by MIPS32 Release 5 are those required for the feature XPA, and those registers are identical to the same registers in the MIPS64 architecture, other than EntryLo0 or the EntryLo1.

If access to Coprocessor 0 is not enabled, a Coprocessor Unusable Exception is signaled.

Operation:

if IsCoprocessorEnabled(0) then
   data = GPR[rt]
   reg = rs
   if (reg,sel = EntryLo1 or reg,sel = EntryLo0) then
      if (Root.Config3LPA = 1 and Root.PageGrainELPA = 1) then // PABITS > 36
         Guest.CPR[0,reg,sel]31..30 = data1..0
         Guest.CPR[0,reg,sel]61:32 = data31..2 and ((1<<(PABITS-36))-1)
         Guest.CPR[0,reg,sel]61:32 = 02
      endif
   else
   endif
else
   SignalException(CoprocessorUnusable, 0)
endif

Exceptions:

Coprocessor Unusable

Reserved Instruction