Encoding:

Format:

MULQ_S.PH rd, rs, rt

Purpose:

Multiply Vector Fractional Half-Words to Same Size Products

Multiply two vector fractional Q15 values to create a Q15 result, with saturation.

Description:

rd = sign_extend(sat16(rs31..16 * rt31..16) || sat16(rs15..0 * rt15..0))

The two right-most vector fractional Q15 values in register rs are multiplied with the corresponding elements in register rt to produce two 32-bit products. Each product is left-shifted by one bit position to create a Q31 fractional word intermediate result. The two 32-bit intermediate results are then each truncated by discarding the 16 least-significant bits of each result, and the resulting Q15 fractional format halfwords are then written to the corresponding positions in destination register rd. For each halfword result, if both input multiplicands are equal to -1 (0x8000 hexadecimal), the final halfword result is saturated to the maximum positive Q15 value (0x7FFF hexadecimal).

The sign of the left-most halfword result is extended into the 32 most-significant bits of the destination register.

To stay compliant with the base architecture, this instruction leaves the base HI/LO pair (accumulator ac0) UNPREDICTABLE after the operation completes. The other DSP Module accumulators

, ac1, ac2, and ac3, must be untouched.

This instruction, on an overflow or underflow of any one of the two vector operation, writes bit 21 in the ouflag field in the DSPControl register.

Restrictions:

No data-dependent exceptions are possible.

The operands must be a value in the specified format. If they are not, the results are UNPREDICTABLE and the values of the operand vectors become UNPREDICTABLE.

Operation:

tempB31..0 = sat16MultiplyQ15Q15( GPR[rs]31..16, GPR[rt]31..16 )
tempA31..0 = sat16MultiplyQ15Q15( GPR[rs]15..0, GPR[rt]15..0 )
GPR[rd]63..0 = (tempB15)32 || tempB15..0 || tempA15..0 
HI[0]63..0 = UNPREDICTABLE
LO[0]63..0 = UNPREDICTABLE
function sat16MultiplyQ15Q15( a15..0, b15..0 )
   if ( a15..0 = 0x8000 ) and ( b15..0 = 0x8000 ) then
      temp31..0 = 0x7FFF0000
      DSPControlouflag:21 = 1
   else
      temp31..0 = ( a15..0 * b15..0 )
      temp31..0 = ( temp30..0 || 0 )
   endif
   return temp31..16
endfunction sat16MultiplyQ15Q15

Exceptions:

Reserved Instruction, DSP Disabled

Programming Notes:

The base MIPS64 architecture states that after a GPR-targeting multiply instruction such as MUL, the contents of registers HI and LO are UNPREDICTABLE. To maintain compliance with the base architecture, this multiply instruction, MULQ_S.PH, has the same requirement. Software must save and restore the ac0 register if the previous value in the ac0 register is needed following the MULQ_S.PH instruction.

Note that the requirement on HI and LO does not apply to the new accumulator registers ac1, ac2, and ac3; as a result, the values in these accumulators need not be saved.