Encoding:

Format:

GINVT rs, type

Purpose:

Global Invalidate TLB

In a multi-processor system, invalidate translations of remote TLBs and local TLB.

Description:

 Invalidate_TLB(GPR[rs], MemoryMapID)

Invalidate a TLB in multiple ways - entire TLB, by Virtual Address and MemoryMapID, by MemoryMapID or Virtual Address. The Virtual Address is obtained from GPR[rs]. The MemoryMapID is derived from CP0

MemoryMapID. The virtual address is associated with a specific Memory Map identified by MemoryMapID.

The virtual address within GPR[rs] is aligned to twice the size of the minimum page size of 4KB i.e., it is equivalent to EntryHiVPN2: bit 13 of the virtual address is aligned to bit 13 of GPR[rs]. If the virtual address is not required, such as in the case of invalidate All or by MemoryMapID, then 'rs' should be specified as 0 in the assembly syntax but is otherwise ignored.

The MemoryMapID is a replacement for EntryHi_ASID. The MemoryMapID is an implementation-dependent number of bits that must be larger than the existing EntryHiASID (10-bits including EntryHiASIDX ). The purpose of a larger tag is to be able to uniquely identify processes in the system. A 16-bit MemoryMapID for example will identify 64K Memory Maps, while the current 8-bit ASID only identifies 256, and is thus subject to frequent recycling.

An implementation with MemoryMapID is designed to be backward compatible with software that uses EntryHi_ASID. See CP0 MemoryMapID.

Table 5.1 specifies the different types of invalidates supported as a function of the "type" field of the instruction.

Table 5.1 Types of Global TLB Invalidates

With reference to Table 5.1, if the Global bit in a TLB entry is set, then MemoryMapID comparison is ignored by the operation.

The instruction is considered complete when the local and remote invalidations are complete. Whether these invalidations are complete can only be determined by the completion of a SYNC (stype=0x14) that follows the invalidate

instruction(s). With the completion of the SYNC operation, all invalidations of this type preceding the SYNC in the program are considered globally visible.

Whether the SYNC(stype=0x14) or the global invalidate itself cause synchronization of the instruction stream to new state/context is implementation dependent.

A GINVT based invalidation is complete, whether local or remote, when the following has occurred: the TLB is invalidated of matching entries, and all instructions in the instruction stream after the point of completion can only access the new context.

A processor may send a global invalidate instruction remotely only when any preceding global invalidate for the program has reached a global ordering point.

GINVT has no instruction or execution hazard barrier semantics in itself.

A GINVT operation that is specified to invalidate all entries will only invalidate non-wired entries. Other GINVT operations will invalidate wired entries on a match.

Restrictions:

If an implementation does not support the instruction, or use of MemoryMapID is disabled, then a Reserved Instruction exception is caused.

If access to Coprocessor 0 is not enabled, a Coprocessor Unusable exception is signaled.

In a single processor SOC, this instruction acts on the local TLB only.

Operation:

Local:
   if (Config5GI != 2'b11) then
      SignalException(ReservedInstruction, 0)
      break
   endif
   if IsCoprocessorEnabled(0) then
      if (Config5MI = 1)
         // generate control from instruction encoding.
         invAll = (ginvt[type] = 0b00)
         invVA = (ginvt[type] = 0b01)
         invMMid = (ginvt[type] = 0b10)
         invVAMMid = (ginvt[type] = 0b11)
         // generate data; how data is driven when unsupported is imp-dep.
         // Format of GPR[rs] equals CP0 EntryHi.
         InvMsgVPN2 = GPR[rs]VPN2msb..13            // VPN2msb is imp-dep in MIPS64
         InvMsgR = GPR[rs]63:62                   // R same as CP0 EntryLo.R
         InvMsgMMid = MemoryMapID                // imp-dep # of bits
         // Broadcast invalidation message to other cores.
         InvalidateTLB(InvMsgVPN2,InvMsgR,InvMsgMMid,invAll,invVAMMid,invMMid,invVA)
      else // if not implemented, MMid disabled
         SignalException(ReservedInstruction)
      endif
   else
      SignalException(CoprocessorUnusable, 0)
   endif
Remote:
      // Repeat in all remote TLBs
      InvalidateTLB(InvMsgVPN2,InvMsgR,InvMsgMMid,invAll,invVAMMid,invMMid,invVA)
function InvalidateTLB(InvMsgVPN2,InvMsgR,InvMsgMMid,invAll,invVAMMid,invMMid,invVA)
      // "Mask" is equivalent to CP0 PageMask.
      // "G" is equivalent to the Global bit in CP0 EntryLo0/1.
      // "R" is equivalent to the R bit in CP0 EntryHi.
      for i in 0..TLBEntries-1 
          // Wired entries are excluded.
          VAMatch = (((TLB[i]VPN2 and not TLB[i]Mask) = (InvMsgVPN2 and not 
TLB[i]Mask)) and (TLB[i]R = InvMsgR))
          MMidMatch = (TLB[i]MMid  =  InvMsgMMid)
          if ((invAll and (i>CP0.Wired.Wired)) or // do not invalidate Wired
         (VAMatch and ((TLB[i]G = 1) or MMidMatch) and invVAMMid) or
         (VAMatch and invVA) or
         (MMidMatch and (TLB[i]G != 1) and invMMid)) then
             TLB[i]HW_Valid = 0       // where HW_Valid is the entry valid bit
         endif
      endfor
endfunction

Exceptions:

Reserved Instruction, Coprocessor Unusable

Programming Notes:

Since CP0 MemoryMapID sources the value of MemoryMapID of the currently running process, the kernel must save/ restore MemoryMapID appropriately before it modifies it for the invalidation operation. Between the save and restore, it must utilize unmapped addresses.

An MTC0 that modifies MemoryMapID must be followed by an EHB to make this value visible to a subsequent

GINVT. Where multiple GINVTs are used prior to a single SYNC (stype=0x14), each may use a different value of

MemoryMapID.

For the local processor, the instruction stream is synchronized to the new translation context (where applicable) by an instruction hazard barrier such as JR.HB.

The instruction stream in the remote processor is synchronized with respect to the execution of GINVT once the

SYNC operation completes.

The following sequence is recommended for use of GINVT.

mtc0 0, C0_PWCtl /* disable Page Walker,where applicable;implementation-dependent*/
ehb             /* Clear execution hazards to prevent speculative walks*/
ginvt r1, type  /* Invalidate TLB(s) */
sync 0x14       /* Enforce completion */
jr.hb ra        /* Clear instruction hazards */

Whether the hardware page table walker, if implemented, needs to be disabled as shown above, is implementation dependent. It is recommended that hardware take the steps to locally disable the hardware page table walker to maintain TLB consistency, as it would for remote TLBs.

Software must take into account a system that may have potentially varying widths of MemoryMapID . While not recommended, different processors may have different implemented or programmed widths. Further, the interface between processors may support yet another width. If this is the case, then software responsible for global invalidates should be run on the processor with maximum width. Software must zero-fill any bits that are unused by a target.

Software should also be able to rely on the implementation zero-filling bits where widths increase across any interface.

If an intermediate interface between source and target truncates the width of MemoryMapID, then software could address this limitation through various means: It could restrict the use of MemoryMapID to the interface width, it could program MemoryMapID with the expectation that over-invalidation may occur, or it should default to legacy means of invalidating the caches to prevent unreliable system behavior.