BNEZC16 101011 |
rs |
offset |
6 |
3 |
7 |
BNEZC16 rs, offset |
microMIPS Release 6 |
Branch on Not Equal to Zero Compact (16-bit instr size) |
Branch on Not Equal to Zero Compact (16-bit instr size)
To compare a GPR to zero then do a PC-relative conditional branch
if GPR[rs] != 0 then branch
A 8-bit signed offset (the 7-bit offset field shifted left 1 bits) is added to the address of the instruction following the branch (not the branch itself), to form a PC-relative effective target address.
If the contents of GPR rs does not equal zero, branch to the effective target address.
Compact branches do not have delay slots. The instruction after the branch is NOT executed if the branch is taken.
The 3-bit register field can only specify GPRs $2-$7, $16, $17.
Any instruction, including a branch or jump, may immediately follow a branch or jump, that is, delay slot restrictions do not apply in Release 6.
target_offset = sign_extend(offset || 0) condition = (GPR[rs] != 0) if condition then PC = PC + target_offset endif
None
With the 8-bit signed instruction offset, the conditional branch range is ± 64 Bytes. Use 32-bit branch, jump (JRC16 or JIC) instructions to branch to addresses outside this range.