Encoding:

POOL32A

rt

rs

rd

0

SHRAV_R.W

1011010101

6

5

5

5

1

10

SPECIAL3

011111

rs

rt

rd

SHRAV_R.W

10111

SHLL.QB

010011

6

5

5

5

5

6

Format: 

SHRAV_R.W rd, rt, rs

microMIPSDSP

Shift Right Arithmetic Variable Word with Rounding

Purpose:

Shift Right Arithmetic Variable Word with Rounding

Arithmetic right shift with rounding of a signed 32-bit word by a variable number of bits.

Description: 

rd = sign_extend(rnd32(rt31..0 >> rs4..0))

The right-most word value in register rt is shifted right, with the value's original sign bit duplicated into the most-significant bits emptied by the shift. A 1 is then added at the most-significant discarded bit position before the result is sign-extended and written to destination register rd.

The shift amount sa is given by the five least-significant bits of register rs; the remaining bits of rs are ignored.

Restrictions:

No data-dependent exceptions are possible.

The operands must be values in the specified format. If they are not, the results are UNPREDICTABLE and the values of the operand vectors become UNPREDICTABLE.

Operation: 

temp31..0 = rnd32ShiftRightArithmetic( GPR[rt]31..0, GPR[rs]4..0 )
GPR[rd]63..0 = (temp31)32 || temp31..0

Exceptions:

Reserved Instruction, DSP Disabled