Encoding:

Format:

DPSQ_SA.L.W ac, rs, rt 

Purpose:

Dot Product with Subtraction on Fractional Word Element

Multiplication of two fractional word elements, subtracting the accumulated product from the specified 64-bit accumulator register, with saturation.

Description:

ac = sat64(ac - sat32(rs31..0 * rt31..0))

The two right-most Q31 fractional word values from registers rt and rs are multiplied together and the result leftshifted by one bit position to generate a 64-bit Q63 fractional format intermediate product. If both multiplicands are equal to -1.0 (0x80000000 hexadecimal), the intermediate product is saturated to the maximum positive Q63 fractional value (0x7FFFFFFFFFFFFFFF hexadecimal).

The intermediate product is then subtracted from the specified 64-bit HI/LO accumulator, creating a Q63 fractional result. If the accumulation results in overflow or underflow, the accumulator is saturated to either the maximum positive or minimum negative Q63 fractional value (0x8000000000000000 hexadecimal), respectively.

The value of ac can range from 0 to 3; a value of 0 refers to the original HI/LO register pair of the MIPS64 architecture.

If saturation occurs, a 1 is written to one of bits 16 through 19 of the DSPControl register, within the ouflag field. The value of ac determines which of these bits is set: bit 16 corresponds to ac0, bit 17 to ac1, bit 18 to ac2, and bit 19 to

ac3.

Restrictions:

No data-dependent exceptions are possible.

The operands must be values in the specified format. If they are not, the result is UNPREDICTABLE and the values of the operand vectors become UNPREDICTABLE.

Operation:

dotp63..0 = multiplyQ31Q31( ac, GPR[rs]31..0, GPR[rt]31..0 )
temp64..0 = HI[ac]31 || HI[ac]31..0 || LO[ac]31..0
temp64..0 = temp - dotp63..0
if ( temp64 != temp63 ) then
   if ( temp64 = 1 ) then
      temp63..0 = 0x8000000000000000
   else
      temp63..0 = 0x7FFFFFFFFFFFFFFF
   endif
   DSPControlouflag:16+ac = 1
endif
( HI[ac]63..0 || LO[ac]63..0 )  = (temp63)32 || temp63..32 || (temp31)32 || temp31..0 

Exceptions:

Reserved Instruction, DSP Disabled