Encoding:

POOL32B

001000

reglist

base

LWM32

0101

offset

6

5

5

4

12

Format: 

LWM32 {sre16, } {ra}, offset(base)

microMIPS

Load Word Multiple

Purpose:

Load Word Multiple

To load a sequence of consecutive words from memory

Description: 

 {GPR[16],{GPR[17],{GPR[18],{GPR[19],{GPR[20],{GPR[21],{GPR[22],{GPR[23],{GPR[30]}}}}}}}}}{GPR[31]} = 
memory[GPR[base]+offset],...,memory[GPR[base]+offset+4*(fn(reglist))]

The contents of consecutive 32-bit words at the memory location specified by the 32-bit aligned effective address are fetched, sign-extended to the GPR register length if necessary, and placed in the GPRs defined by reglist. The 12-bit signed offset is added to the contents of GPR base to form the effective address.

The following table shows the encoding of the reglist field.

reglist Encoding

(binary)

List of Registers Loaded

0 0 0 0 1

GPR[16]

0 0 0 1 0

GPR[16], GPR[17]

0 0 0 1 1

GPR[16], GPR[17], GPR[18]

0 0 1 0 0

GPR[16], GPR[17], GPR[18], GPR[19]

0 0 1 0 1

GPR[16], GPR[17], GPR[18], GPR[19], GPR[20]

0 0 1 1 0

GPR[16], GPR[17], GPR[18], GPR[19], GPR[20], GPR[21]

0 0 1 1 1

GPR[16], GPR[17], GPR[18], GPR[19], GPR[20], GPR[21], GPR[22]

0 1 0 0 0

GPR[16], GPR[17], GPR[18], GPR[19], GPR[20], GPR[21], GPR[22], GPR[23]

0 1 0 0 1

GPR[16], GPR[17], GPR[18], GPR[19], GPR[20], GPR[21], GPR[22], GPR[23], GPR[30]

1 0 0 0 0

GPR[31]

1 0 0 0 1

GPR[16], GPR[31]

1 0 0 1 0

GPR[16], GPR[17], GPR[31]

1 0 0 1 1

GPR[16], GPR[17], GPR[18], GPR[31]

1 0 1 0 0

GPR[16], GPR[17], GPR[18], GPR[19], GPR[31]

1 0 1 0 1

GPR[16], GPR[17], GPR[18], GPR[19], GPR[20], GPR[31]

1 0 1 1 0

GPR[16], GPR[17], GPR[18], GPR[19], GPR[20], GPR[21], GPR[31]

1 0 1 1 1

GPR[16], GPR[17], GPR[18], GPR[19], GPR[20], GPR[21], GPR[22], GPR[31]

1 1 0 0 0

GPR[16], GPR[17], GPR[18], GPR[19], GPR[20], GPR[21], GPR[22], GPR[23], GPR[31]

1 1 0 0 1

GPR[16], GPR[17], GPR[18], GPR[19], GPR[20], GPR[21], GPR[22], GPR[23], GPR[30], GPR[31]

All other combinations

Reserved

The register numbers and the effective addresses are correlated using the order listed in the table, starting with the left-most register on the list and ending with the right-most register on the list. The effective address is incremented for each subsequent register on the list.

It is implementation-specific whether interrupts are disabled during the sequence of operations generated by this instruction.

Restrictions:

The behavior of the instruction is UNPREDICTABLE, if base is included in reglist. Reason for this is to allow restartability of the operation if an interrupt or exception has aborted the operation in the middle.

Pre-Release 6: The effective address must be 32-bit aligned. If either of the 2 least-significant bits of the address is non-zero, an Address Error exception occurs.

Release 6 allows hardware to provide address misalignment support in lieu of requiring natural alignment.

Note: The pseudocode is not completely adapted for Release 6 misalignment support as the handling is implementation dependent.

Operation: 

vAddr = sign_extend(offset) + GPR[base]
for i=0 to fn(reglist)
   (pAddr, CCA) = AddressTranslation (vAddr, DATA, LOAD)
   pAddr = pAddrPSIZE-1..3 || (pAddr2..0 xor (ReverseEndian || 02))
   memdoubleword = LoadMemory (CCA, WORD, pAddr, vAddr, DATA)
   byte = vAddr2..0 xor (BigEndianCPU || 02)
   GPR[gpr(reglist,i)] = sign_extend(memdoubleword31+8*byte..8*byte)
   vAddr = vAddr + 4
endfor
function fn(list)
   fn = (number of entries in list) - 1 
endfunction

Exceptions:

TLB Refill, TLB Invalid, Bus Error, Address Error, Watch