Encoding:

Format:

CMP.condn.fmt 

CMP.condn.S fd, fs, ft

CMP.condn.D fd, fs, ft

Purpose:

Floating Point Compare Setting Mask

To compare FP values and record the result as a format-width mask of all 0s or all 1s in a floating point register

Description:

 FPR[fd] = FPR[fs] compare_cond FPR[ft]

The value in FPR fs is compared to the value in FPR ft.

The comparison is exact and neither overflows nor underflows.

If the comparison specified by the condn field of the instruction is true for the operand values, the result is true; otherwise, the result is false. If no exception is taken, the result is written into FPR fd; true is all 1s and false is all 0s, repeated the operand width of fmt. All other bits beyond the operand width fmt are UNPREDICTABLE. For example, a 32-bit single precision comparison writes a mask of 32 0s or 1s into bits 0 to 31 of FPR fd. It makes bits 32 to 63

UNPREDICTABLE if a 64-bit FPU without MSA is present. It makes bits 32 to 127 UNPREDICTABLE if MSA is present.

The values are in format fmt. These instructions, however, do not use an fmt field to determine the data type.

The condn field of the instruction specifies the nature of the comparison: equals, less than, and so on, unordered or ordered, signalling or quiet, as specified in Table 5.23 "Comparing CMP.condn.fmt, IEEE 754-2008, C.cond.fmt, and MSA FP compares" on page 181.

Release 6: The condn field bits have specific purposes: cond₄, and cond_2..1 specify the nature of the comparison

(equals, less than, and so on); cond₀ specifies whether the comparison is ordered or unordered, that is false or true if any operand is a NaN; cond3 indicates whether the instruction should signal an exception on QNaN inputs. However, in the future the MIPS ISA may be extended in ways that do not preserve these meanings.

All encodings of the condn field that are not specified (for example, items shaded in Table 5.23) are reserved in

Release 6 and produce a Reserved Instruction exception.

If one of the values is an SNaN, or if a signalling comparison is specified and at least one of the values is a QNaN, an

Invalid Operation condition is raised and the Invalid Operation flag is set in the FCSR. If the Invalid Operation

Enable bit is set in the FCSR, no result is written and an Invalid Operation exception is taken immediately. Otherwise,

the mask result is written into FPR fd.

There are four mutually exclusive ordering relations for comparing floating point values; one relation is always true and the others are false. The familiar relations are greater than, less than, and equal. In addition, the IEEE floating point standard defines the relation unordered, which is true when at least one operand value is NaN; NaN compares unordered with everything, including itself. Comparisons ignore the sign of zero, so +0 equals -0.

The comparison condition is a logical predicate, or equation, of the ordering relations such as less than or equal,

equal, not less than, or unordered or equal. Compare distinguishes among the 16 comparison predicates. The Boolean result of the instruction is obtained by substituting the Boolean value of each ordering relation for the two FP values in the equation. For example: If the equal relation is true, then all four example predicates above yield a true

result. If the unordered relation is true then only the final predicate, unordered or equal, yields a true result.

The predicates implemented are described in Table 5.23 "Comparing CMP.condn.fmt, IEEE 754-2008, C.cond.fmt, and MSA FP compares" on page 181. Not all of the 16 IEEE predicates are implemented directly by hardware. For the directed comparisons (LT, LE, GT, GE) the missing predicates can be obtained by reversing the FPR register operands ft and fs. For example, the hardware implements the "Ordered Less Than" predicate LT(fs,ft); reversing the operands LT(ft,fs) produces the dual predicate "Unordered or Greater Than or Equal" UGE(fs,ft). Table 5.23 shows these mappings. Reversing inputs is ineffective for the symmetric predicates such as EQ; Release 6 implements these negative predicates directly, so that all mask values can be generated in a single instruction.

Table 5.23 compares CMP.condn fmt to (1) the MIPS32 Pre-Release 6 C.cond fmt instructions, and (2) the (MSA)

MIPS SIMD Architecture packed vector floating point comparison instructions. CMP.condn fmt provides exactly the same comparisons for FPU scalar values that MSA provides for packed vectors, with similar mnemonics.

CMP.condn fmt provides a superset of the MIPS32 Release 5 C.cond fmt comparisons.

In addition, Table 5.23 shows the corresponding IEEE 754-2008 comparison operations.

Restrictions:

Operation:

if SNaN(ValueFPR(fs, fmt)) or SNaN(ValueFPR(ft, fmt)) or
   QNaN(ValueFPR(fs, fmt)) or QNaN(ValueFPR(ft, fmt)) 
then
   less = false
   equal = false
   unordered = true
   if (SNaN(ValueFPR(fs,fmt)) or SNaN(ValueFPR(ft,fmt))) or
      (cond3 and (QNaN(ValueFPR(fs,fmt)) or QNaN(ValueFPR(ft,fmt)))) then
          SignalException(InvalidOperation)
   endif
   else
      less = ValueFPR(fs, fmt) <fmt ValueFPR(ft, fmt)
      equal = ValueFPR(fs, fmt) =fmt ValueFPR(ft, fmt)
      unordered = false
   endif
   condition = cond4 xor (
          (cond2 and less) 
          or (cond1 and equal)
          or (cond0 and unordered) )
   StoreFPR (fd, fmt, ExtendBit.fmt(condition))

Exceptions:

Coprocessor Unusable, Reserved Instruction

Floating Point Exceptions:

Unimplemented Operation, Invalid Operation