Encoding:

Format:

JALRC16 rs 

Purpose:

Jump and Link Register Compact (16-bit instr size)

To execute a procedure call to an instruction address in a register

Description:

 GPR[31] = return_addr, PC = GPR[rs]

For processors that do not implement the MIPS64 ISA:

• Jump to the effective target address in GPR rs. Bit 0 of GPR rs is interpreted as the target ISA Mode: if this bit is 0, signal an Address Error exception when the target instruction is fetched because this target ISA Mode is not supported. Otherwise, set bit 0 of the target address to zero, and fetch the instruction.

For processors that do implement the MIPS64 ISA:

• Jump to the effective target address in GPR rs. Set the ISA Mode bit to the value in GPR rs bit 0. Set bit 0 of the target address to zero. If the target ISA Mode bit is 0 and the target address is not 4-byte aligned, an Address

Error exception will occur when the target instruction is fetched.

Place the return address link in GPR r31. The return link is the address of the first instruction following the branch, where execution continues after a procedure call.

Compact jumps do not have delay slots. The instruction after the jump is NOT executed when the jump is executed.

Restrictions:

If only one instruction set is implemented, then the effective target address must obey the alignment rules of the instruction set. If multiple instruction sets are implemented, the effective target address must obey the alignment rules of the intended instruction set of the target address as specified by the bit 0 or GPR rs.

For processors which implement MIPS64 and if the ISAMode bit of the target is MIPS64 (bit 0 of GPR rs is 0) and address bit 1 is one, an Address Error exception occurs when the jump target is subsequently fetched as an instruction.

For processors that do not implement MIPS64 ISA, if the intended target ISAMode is MIPS64 (bit 0 of GPR rs is zero), an Address Error exception occurs when the jump target is fetched as an instruction.

Any instruction, including a branch or jump, may immediately follow a branch or jump; that is, delay slot restrictions do not apply in Release 6.

Operation:

temp = GPR[rs]
   GPR[31] = PC + 2
if Config3ISA = 1 then
      PC = temp
   else
      PC = tempGPRLEN-1..1 || 0
      ISAMode = temp0
   endif

Exceptions:

None