Encoding:

Format:

MULSAQ_S.W.PH ac, rs, rt

Purpose:

Multiply And Subtract Vector Fractional Halfwords And Accumulate

Multiply and subtract two Q15 fractional halfword vector elements using full-size intermediate products, accumulating the result from the specified accumulator, with saturation.

Description:

ac = ac + (sat32(rs31..16 * rt31..16) - sat32(rs15..0 * rt15..0))

The two corresponding right-most Q15 fractional values from registers rt and rs are multiplied together and leftshifted by 1 bit to generate two Q31 fractional format intermediate products. If the input multiplicands to either of the multiplications are both -1.0 (0x8000 hexadecimal), the intermediate result is saturated to 0x7FFFFFFF hexadecimal.

The two intermediate products (named left and right) are summed with alternating sign to create a sum-of-products, i.e., the sign of the right product is negated before summation. The sum-of-products is then sign-extended to 64 bits and accumulated into the specified 64-bit accumulator, producing a Q32.31 result.

The value of ac can range from 0 to 3; a value of 0 refers to the original HI/LO register pair of the MIPS64 architecture.

If saturation occurs, a 1 is written to one of bits 16 through 19 of the DSPControl register, within the ouflag field. The value of ac determines which of these bits is set: bit 16 corresponds to ac0, bit 17 to ac1, bit 18 to ac2, and bit 19 to

ac3.

Restrictions:

No data-dependent exceptions are possible.

The operands must be values in the specified format. If they are not, the results are UNPREDICTABLE and the values of the operand vectors become UNPREDICTABLE.

Operation:

tempB31..0 = multiplyQ15Q15( ac, rs31..16, rt31..16 )
tempA31..0 = multiplyQ15Q15( ac, rs15..0, rt15..0 )
dotp63..0 = ( (tempB31)32 || tempB31..0 ) - ( (tempA31)32 || tempA31..0 )
tempC63..0 = ( HI[ac]31..0 || LO[ac]31..0 ) + dotp63..0
( HI[ac]63..0 || LO[ac]63..0 ) = (tempC63)32 || tempC63..32 || (tempC31)32 || tempC31..0

Exceptions:

Reserved Instruction, DSP Disabled