Encoding:

Format:

LLDP rt, rd, (base)

Purpose:

Load Linked DoubleWord Paired

To load two double-words from memory for an atomic read-modify-write, writing a double-word each to two registers.

Description:

 GPR[rd] = memory[GPR[base]]127..64, GPR[rt] = memory[GPR[base]]63..0

The LLDP and SCDP instructions provide primitives to implement a paired double-word atomic read-modify-write

(RMW) operation at a synchronizable memory location.

The paired double-word at the memory location specified by the quad-word aligned effective address is read in a single atomic memory operation. The least significant double-word is written into GPR rt. The most significant doubleword is written into GPR rd.

A paired double-word read or write occurs as a pair of double-word reads or writes that is quad-word atomic.

The instruction has no offset. The effective address is equal to the contents of GPR base.

rd is intentionally positioned in a non-standard bit-range.

The execution of LLDP begins a RMW sequence on the current processor. There can be only one active RMW sequence per processor. When an LLDP is executed it starts an active RMW sequence replacing any other sequence that was active. The RMW sequence is completed by a subsequent SCDP instruction that either completes the RMW sequence atomically and succeeds, or does not and fails.

Successful execution of the LLDP results in setting LLbit and writing CP0 LLAddr, where LLbit is the least-significant bit of LLAddr. LLAddr contains the data-type aligned address of the operation, in this case a quad-word aligned address.

Executing LLDP on one processor does not cause an action that, by itself, causes a store conditional instruction type for the same block to fail on another processor.

An execution of LLDP does not have to be followed by execution of SCDP; a program is free to abandon the RMW sequence without attempting a write.

Restrictions:

The addressed location must be synchronizable by all processors and I/O devices sharing the location; if it is not, the result is UNPREDICTABLE. Which storage is synchronizable is a function of both CPU and system implementations. See the documentation of the SC instruction for the formal definition.

The architecture optionally allows support for Load-Linked and Store-Conditional instruction types in a cacheless processor. Support for cacheless operation is implementation dependent. In this case, LLAddr is optional.

Providing misaligned support is not a requirement for this instruction.

Availability and Compatibility

This instruction is introduced by Release 6. It is only present if Config5_XNP=0.

Operation:

vAddr = GPR[base]
(pAddr, CCA) = AddressTranslation (vAddr, DATA, LOAD)
// PAIREDDOUBLEWORD: two double-word data-type that is quad-word atomic
memquadword = LoadMemory (CCA, PAIREDDOUBLEWORD, pAddr, vAddr, DATA)
GPR[rt] = memquadword63..0
GPR[rd] = memquadword127..64
LLAddr = pAddr // quad-word aligned i.e., pAddr3..0 are 0, or not supported.
LLbit = 1

Exceptions:

TLB Refill, TLB Invalid, Reserved Instruction, Address Error, Watch

Programming Notes:

An LLDP instruction for which the two destination registers are the same but non-zero is UNPREDICTABLE. An

LLDP with two zero destination registers followed by a SCDP can be used to accomplish a quad-word atomic write.