Encoding:

POOL32A

000000

rt

rs

rd

0

PACKRL.PH

0110101101

6

5

5

5

1

10

SPECIAL3

011111

rs

rt

rd

PACKRL.PH

01110

CMPU.EQ.QB

010001

6

5

5

5

5

6

Format: 

PACKRL.PH rd, rs, rt

microMIPSDSP

Pack a Vector of Halfwords from Vector Halfword Sources

Purpose:

Pack a Vector of Halfwords from Vector Halfword Sources

Pick two elements for a halfword vector using the right halfword and left halfword respectively from the two source registers.

Description: 

rd = sign_extend(rs15..0 || rt31..16)

The right-most halfword element from register rs and the left halfword from the two right-most halfwords in register

rt are packed into the two right-most halfword positions of the destination register rd.

The sign of the left-most halfword result is extended into the 32 most-significant bits of the destination register.

Restrictions:

No data-dependent exceptions are possible.

The operands must be values in the specified format. If they are not, the results are UNPREDICTABLE and the values of the operand vectors become UNPREDICTABLE.

Operation: 

tempB15..0 = GPR[rs]15..0
tempA15..0 = GPR[rt]31..16
GPR[rd]63..0 = (tempB15)32 || tempB15..0 || tempA15..0

Exceptions:

Reserved Instruction, DSP Disabled