Encoding:

Format:

MSUBU ac, rs, rt

Purpose:

Multiply Unsigned Word and Add to Accumulator

To multiply two 32-bit unsigned integer words and subtract the 64-bit result from the specified accumulator.

Description:

 (HI[ac]||LO[ac]) = (HI[ac]||LO[ac]) - (rs31..0 * rt31..0)

The 32-bit unsigned integer word in register rs is multiplied by the corresponding 32-bit unsigned integer word in register rt to produce a 64-bit result. The 64-bit product is subtracted from the specified 64-bit accumulator.

These special registers HI and LO are specified by the value of ac. When ac=0, this refers to the original HI/LO register pair of the MIPS64 architecture.

In Release 6 of the MIPS Architecture, accumulators are eliminated from MIPS64.

No arithmetic exception occurs under any circumstances.

Restrictions:

If registers rs or rt do not contain sign-extended 32-bit values (i.e., bits 31 through 63 are equal), then the results of the operation are UNPREDICTABLE.

This instruction does not provide the capability of writing directly to a target GPR.

Operation:

if NotWordValue(GPR[rs]) or NotWordValue(GPR[rt])) then
   UNPREDICTABLE 
endif
temp64..0 = (032 || GPR[rs]31..0 ) * ( 032 || GPR[rt]31..0 )
acc63..0 = ( HI[ac]31..0 || LO[ac]31..0 ) - temp63..0
( HI[ac]63..0 || LO[ac]63..0 ) = (acc63)32 || acc63..32 || (acc31)32 || acc31..0

Exceptions:

Reserved Instruction, DSP Disabled

Programming Notes:

In some processors the integer multiply operation may proceed asynchronously and allow other CPU instru ctions to execute before it is complete. An attempt to read LO or HI before the results are written interlocks until the results are ready. Asynchronous execution does not affect the program result, but offers an op portunity for performance improvement by scheduling the multiply so that other instructions can execute in parallel.

Programs that require overflow detection must check for it explicitly.

Where the size of the operands are known, software should place the shorter operand in register rt. This may reduce the latency of the instruction on those processors which implement data-dependent instruction latencies.