Encoding:

Format:

CTC1 rt, fs

Purpose:

Move Control Word to Floating Point

To copy a word from a GPR to an FPU control register.

Description:

 FP_Control[fs] = GPR[rt]

Copy the low word from GPR rt into the FP (coprocessor 1) control register indicated by fs.

Writing to the floating point Control/Status register, the FCSR, causes the appropriate exception if any Cause bit and its corresponding Enable bit are both set. The register is written before the exception occurs. Writing to FEXR to set a cause bit whose enable bit is already set, or writing to FENR to set an enable bit whose cause bit is already set causes the appropriate exception. The register is written before the exception occurs and the EPC register contains the address of the CTC1 instruction.

The definition of this instruction has been extended in Release 5 to support user mode read and write of Status_FR under the control of Config5UFR. This optional feature is meant to facilitate transition from FR=0 to FR=1 floating-point register modes in order to obsolete FR=0 mode in a future architecture release. User code may set and clear Status_FR without kernel intervention, providing kernel explicitly provides permission.

This UFR facility is not supported in Release 6 since Release 6 only allows FR=1 mode. Accessing the UFR and

UNFR registers causes a Reserved Instruction exception in Release 6 since FIR_UFRP is always 0.

The definition of this instruction has been extended in Release 6 to allow user code to read and modify the Config5_FRE bit. Such modification is allowed when this bit is present (as indicated by FIR_UFRP) and user mode

modification of the bit is enabled by the kernel (as indicated by Config5_UFE). Setting Config5_FRE to 1 causes all floating point instructions which are not compatible with FR=1 mode to take an Reserved Instruction exception. This makes it possible to run pre-Release 6 FR=0 floating point code on a Release 6 core which only supports FR=1 mode, provided the kernel has been set up to trap and emulate FR=0 behavior for these instructions. These instructions include floating-point arithmetic instructions that read/write single-precision registers, LWC1, SWC1, MTC1, and

MFC1 instructions.

The FRE facility uses COP1 register aliases FRE and NFRE to access Config5_FRE.

Restrictions:

There are a few control registers defined for the floating point unit. Prior to Release 6, the result is UNPREDICTABLE if fs specifies a register that does not exist. In Release 6 and later, a Reserved Instruction exception occurs if fs specifies a register that does not exist.

Furthermore, the result is UNPREDICTABLE if fd specifies the UFR, UNFR, FRE and NFRE aliases, with fs anything other than 00000, GPR[0]. Release 6 implementations and later are required to produce a Reserved Instruction exception; software must assume it is UNPREDICTABLE.

Operation:

temp = GPR[rt]31..0
if (fs = 1 or fs = 4) then
   /* clear UFR or UNFR(CP1 Register 1)*/
   if ConfigAR >= 2 SignalException(ReservedInstruction) /* Release 6 traps */ endif
   if not Config5UFR then SignalException(ReservedInstruction) endif
   if not (rt = 0 and FIRUFRP) then UNPREDICTABLE /*end of instruction*/ endif
   if fs = 1 then StatusFR = 0
   elseif fs = 4 then StatusFR = 1
   else /* cannot happen */
elseif fs=5 then /* user write of 1 to FRE, if permitted */
   if ConfigAR <= 2 then UNPREDICTABLE
   else
      if rt != 0 then SignalException(ReservedInstruction) endif
      if not Config5UFR then SignalException(ReservedInstruction) endif
      Config5UFR = 0
   endif
elseif fs=6 then /* user write of 0 to FRE, if permitted (NFRE alias) */
   if ConfigAR <= 2 then UNPREDICTABLE
   else
      if rt != 0 then SignalException(ReservedInstruction) endif
      if not Config5UFR then SignalException(ReservedInstruction) endif
      Config5UFR = 1
   endif
elseif fs = 25 then /* FCCR */
   if temp31..8 != 024 then
      UNPREDICTABLE
   else
      FCSR = temp7..1 || FCSR24 || temp0 || FCSR22..0
   endif
elseif fs = 26 then /* FEXR */
   if temp31..18 != 0 or temp11..7 != 0 or temp2..0 != 0then
      UNPREDICTABLE
   else
      FCSR = FCSR31..18 || temp17..12 || FCSR11..7 || 
      temp6..2 || FCSR1..0
   endif
elseif fs = 28 then /* FENR */
   if temp31..12 != 0 or temp6..3 != 0 then
      UNPREDICTABLE
   else
      FCSR = FCSR31..25 || temp2 || FCSR23..12 || temp11..7 
      || FCSR6..2 || temp1..0
   endif
elseif fs = 31 then /* FCSR */
   if (FCSRImpl field is not implemented) and(temp22..18 != 0) then 
      UNPREDICTABLE
   elseif (FCSRImpl field is implemented) and temp20..18 != 0 then
      UNPREDICTABLE
   else
      FCSR = temp
   endif
else
   if Config2AR >= 2 SignalException(ReservedInstruction) /* Release 6 traps */
   endif
   UNPREDICTABLE
endif
CheckFPException()

Exceptions:

Coprocessor Unusable, Reserved Instruction

Floating Point Exceptions:

Unimplemented Operation, Invalid Operation, Division-by-zero, Inexact, Overflow, Underflow

Historical Information:

For the MIPS I, II and III architectures, the contents of floating point control register fs are UNPREDICTABLE for the instruction immediately following CTC1.

MIPS V and MIPS32 introduced the three control registers that access portions of FCSR. These registers were not available in MIPS I, II, III, or IV.

MIPS32 Release 5 introduced the UFR and UNFR register aliases that allow user level access to Status_FR.

MIPS32 Release 6 introduced the FRE and NFRE register aliases that allow user to cause traps for FR=0 mode emulation.