MIPS ISA Reference

MD00087-2B-MIPS64BIS-AFP-6.06

ABS.S fd, fs MIPS32 Floating Point Absolute Value
ABS.D fd, fs MIPS32 Floating Point Absolute Value
ABS.PS fd, fs MIPS64, MIPS32 Release 2, removed in Release 6 Floating Point Absolute Value
ADD.S fd, fs, ft MIPS32 Floating Point Add
ADD.D fd, fs, ft MIPS32 Floating Point Add
ADD.PS fd, fs, ft MIPS64, MIPS32 Release 2, removed in Release 6 Floating Point Add
ADDI rt, rs, immediate MIPS32, removed in Release 6 Add Immediate Word
ADDIUPC rs,immediate MIPS32 Release 6 Add Immediate to PC (unsigned - non-trapping)
ADDIU rt, rs, immediate MIPS32 Add Immediate Unsigned Word
ADD rd, rs, rt MIPS32 Add Word
ADDU rd, rs, rt MIPS32 Add Unsigned Word
ALIGN rd,rs,rt,bp MIPS32 Release 6 Concatenate two GPRs, and extract a contiguous subset at a byte position
DALIGN rd,rs,rt,bp MIPS64 Release 6 Concatenate two GPRs, and extract a contiguous subset at a byte position
ALNV.PS fd, fs, ft, rs MIPS64, MIPS32 Release 2, removed in Release 6 Floating Point Align Variable
ALUIPC rs,immediate MIPS32 Release 6 Aligned Add Upper Immediate to PC
ANDI rt, rs, immediate MIPS32 and immediate
AND rd, rs, rt MIPS32 and
AUI rt, rs immediate MIPS32 Release 6 Add Upper Immediate
DAUI rt, rs immediate MIPS64 Release 6 Doubleword Add Upper Immediate
DAHI rs, rs immediate MIPS64 Release 6 Doubleword Add Higher Immediate
DATI rs, rs immediate MIPS64 Release 6 Doubleword Add Top Immediate
AUIPC rs, immediate MIPS32 Release 6 Add Upper Immediate to PC
BALC offset MIPS32 Release 6 Branch and Link, Compact
BAL offset Assembly Idiom MIPS32, MIPS32 Release 6 Branch and Link
BC1EQZ ft, offset MIPS32 Release 6 Branch if Coprocessor 1 (FPU) Register Bit 0 is Equal to Zero
BC1NEZ ft, offset MIPS32 Release 6 Branch if Coprocessor 1 (FPR) Register Bit 0 is Not Equal to Zero
BC1F cc, offset MIPS32, removed in Release 6 Branch on FP False
BC1FL cc, offset MIPS32, removed in Release 6 Branch on FP False Likely
BC1T cc, offset MIPS32, removed in Release 6 Branch on FP True
BC1TL cc, offset MIPS32, removed in Release 6 Branch on FP True Likely
BC2EQZ ct, offset MIPS32 Release 6 Branch if Coprocessor 2 Condition (Register) is Equal to Zero
BC2NEZ ct, offset MIPS32 Release 6 Branch if Coprocessor 2 Condition (Register) is Not Equal to Zero
BC2F cc, offset MIPS32, removed in Release 6 Branch on COP2 False
BC2FL cc, offset MIPS32, removed in Release 6 Branch on COP2 False Likely
BC2T cc, offset MIPS32, removed in Release 6 Branch on COP2 True
BC2TL cc, offset MIPS32, removed in Release 6 Branch on COP2 True Likely
BC offset MIPS32 Release 6 Branch, Compact
BEQL rs, rt, offset MIPS32, removed in Release 6 Branch on Equal Likely
BEQ rs, rt, offset MIPS32 Branch on Equal
BGEZALL rs, offset MIPS32, removed in Release 6 Branch on Greater Than or Equal to Zero and Link Likely
BGEZAL rs, offset MIPS32, removed in Release 6 Branch on Greater Than or Equal to Zero and Link
BGEZL rs, offset MIPS32, removed in Release 6 Branch on Greater Than or Equal to Zero Likely
BGEZ rs, offset MIPS32 Branch on Greater Than or Equal to Zero
BGTZL rs, offset MIPS32, removed in Release 6 Branch on Greater Than Zero Likely
BGTZ rs, offset MIPS32 Branch on Greater Than Zero
BITSWAP rd,rt MIPS32 Release 6 Swaps (reverses) bits in each byte
DBITSWAP rd,rt MIPS64 Release 6 Swaps (reverses) bits in each byte
BLEZL rs, offset MIPS32, removed in Release 6 Branch on Less Than or Equal to Zero Likely
BLEZ rs, offset MIPS32 Branch on Less Than or Equal to Zero
BLTZALL rs, offset MIPS32, removed in Release 6 Branch on Less Than Zero and Link Likely
BLTZAL rs, offset MIPS32, removed in Release 6 Branch on Less Than Zero and Link
BLTZL rs, offset MIPS32, removed in Release 6 Branch on Less Than Zero Likely
BLTZ rs, offset MIPS32 Branch on Less Than Zero
BNEL rs, rt, offset MIPS32, removed in Release 6 Branch on Not Equal Likely
BNE rs, rt, offset MIPS32 Branch on Not Equal
B offset MIPS32, Assembly Idiom Unconditional Branch
BOVC rs,rt,offset MIPS32 Release 6 Detect overflow for add (signed 32 bits) and branch if overflow.
BNVC rs,rt,offset MIPS32 Release 6 Detect overflow for add (signed 32 bits) and branch if no overflow.
BREAK MIPS32 Breakpoint
BEQC rs, rt, offset MIPS32 Release 6 Equal/Not-Equal register-register compare and branch with 16-bit offset:
BNEC rs, rt, offset MIPS32 Release 6 Equal/Not-Equal register-register compare and branch with 16-bit offset:
BLTC rs, rt, offset MIPS32 Release 6 Signed register-register compare and branch with 16-bit offset:
BGEC rs, rt, offset MIPS32 Release 6 Signed register-register compare and branch with 16-bit offset:
BLTUC rs, rt, offset MIPS32 Release 6 Unsigned register-register compare and branch with 16-bit offset:
BGEUC rs, rt, offset MIPS32 Release 6 Unsigned register-register compare and branch with 16-bit offset:
BGTC rt, rs, offset Assembly Idiom Assembly idioms with reversed operands for signed/unsigned compare-and-branch:
BLEC rt, rs, offset Assembly Idiom Assembly idioms with reversed operands for signed/unsigned compare-and-branch:
BGTUC rt, rs, offset Assembly Idiom Assembly idioms with reversed operands for signed/unsigned compare-and-branch:
BLEUC rt, rs, offset Assembly Idiom Assembly idioms with reversed operands for signed/unsigned compare-and-branch:
BLTZC rt, offset MIPS32 Release 6 Signed Compare register to Zero and branch with 16-bit offset:
BLEZC rt, offset MIPS32 Release 6 Signed Compare register to Zero and branch with 16-bit offset:
BGEZC rt, offset MIPS32 Release 6 Signed Compare register to Zero and branch with 16-bit offset:
BGTZC rt, offset MIPS32 Release 6 Signed Compare register to Zero and branch with 16-bit offset:
BEQZC rs, offset MIPS32 Release 6 Equal/Not-equal Compare register to Zero and branch with 21-bit offset:
BNEZC rs, offset MIPS32 Release 6 Equal/Not-equal Compare register to Zero and branch with 21-bit offset:
BLEZALC rt, offset MIPS32 Release 6 Compact branch-and-link if GPR rt is less than or equal to zero
BGEZALC rt, offset MIPS32 Release 6 Compact branch-and-link if GPR rt is greater than or equal to zero
BGTZALC rt, offset MIPS32 Release 6 Compact branch-and-link if GPR rt is greater than zero
BLTZALC rt, offset MIPS32 Release 6 Compact branch-and-link if GPR rt is less than to zero
BEQZALC rt, offset MIPS32 Release 6 Compact branch-and-link if GPR rt is equal to zero
BNEZALC rt, offset MIPS32 Release 6 Compact branch-and-link if GPR rt is not equal to zero
C.cond.S cc, fs, ft MIPS32, removed in Release 6 Floating Point Compare
C.cond.D cc, fs, ft MIPS32, removed in Release 6 Floating Point Compare
C.cond.PS cc, fs, ft MIPS64, MIPS32 Release 2, removed in Release 6 Floating Point Compare
CACHEE op, offset(base) MIPS32 Perform Cache Operation EVA
CACHE op, offset(base) MIPS32 Perform Cache Operation
CEIL.L.S fd, fs MIPS64, MIPS32 Release 2 Fixed Point Ceiling Convert to Long Fixed Point
CEIL.L.D fd, fs MIPS64, MIPS32 Release 2 Fixed Point Ceiling Convert to Long Fixed Point
CEIL.W.S fd, fs MIPS32 Floating Point Ceiling Convert to Word Fixed Point
CEIL.W.D fd, fs MIPS32 Floating Point Ceiling Convert to Word Fixed Point
CFC1 rt, fs MIPS32 Move Control Word From Floating Point
CFC2 rt, Impl MIPS32 Move Control Word From Coprocessor 2
CLASS.S fd,fs MIPS32 Release 6 Scalar Floating-Point Class Mask
CLASS.D fd,fs MIPS32 Release 6 Scalar Floating-Point Class Mask
CLO rd, rs MIPS32 Count Leading Ones in Word
CLZ rd, rs MIPS32 Count Leading Zeros in Word
CMP.condn.S fd, fs, ft MIPS32 Release 6 Floating Point Compare Setting Mask
CMP.condn.D fd, fs, ft MIPS32 Release 6 Floating Point Compare Setting Mask
COP2 func MIPS32 Coprocessor Operation to Coprocessor 2
CRC32B rt, rs, rt MIPS32 Release 6 Generate CRC with reversed polynomial 0xEDB88320
CRC32H rt, rs, rt MIPS32 Release 6 Generate CRC with reversed polynomial 0xEDB88320
CRC32W rt, rs, rt MIPS32 Release 6 Generate CRC with reversed polynomial 0xEDB88320
CRC32D rt, rs, rt MIPS64 Release 6 Generate CRC with reversed polynomial 0xEDB88320
CRC32CB rt, rs, rt MIPS32 Release 6 Generate CRC with reversed polynomial 0x82F63B78
CRC32CH rt, rs, rt MIPS32 Release 6 Generate CRC with reversed polynomial 0x82F63B78
CRC32CW rt, rs, rt MIPS32 Release 6 Generate CRC with reversed polynomial 0x82F63B78
CRC32CD rt, rs, rt MIPS64 Release 6 Generate CRC with reversed polynomial 0x82F63B78
CTC1 rt, fs MIPS32 Move Control Word to Floating Point
CTC2 rt, Impl MIPS32 Move Control Word to Coprocessor 2
CVT.D.S fd, fs MIPS32 Floating Point Convert to Double Floating Point
CVT.D.W fd, fs MIPS32 Floating Point Convert to Double Floating Point
CVT.D.L fd, fs MIPS64, MIPS32 Release 2 Floating Point Convert to Double Floating Point
CVT.L.S fd, fs MIPS64, MIPS32 Release 2 Floating Point Convert to Long Fixed Point
CVT.L.D fd, fs MIPS64, MIPS32 Release 2 Floating Point Convert to Long Fixed Point
CVT.PS.S fd, fs, ft MIPS64, MIPS32 Release 2, removed in Release 6 Floating Point Convert Pair to Paired Single
CVT.S.D fd, fs MIPS32 Floating Point Convert to Single Floating Point
CVT.S.W fd, fs MIPS32 Floating Point Convert to Single Floating Point
CVT.S.L fd, fs MIPS64, MIPS32 Release 2 Floating Point Convert to Single Floating Point
CVT.S.PL fd, fs MIPS64, MIPS32 Release 2, removed in Release 6 Floating Point Convert Pair Lower to Single Floating Point
CVT.S.PU fd, fs MIPS64, MIPS32 Release 2, , removed in Release 6 Floating Point Convert Pair Upper to Single Floating Point
CVT.W.S fd, fs MIPS32 Floating Point Convert to Word Fixed Point
CVT.W.D fd, fs MIPS32 Floating Point Convert to Word Fixed Point
DADDI rt, rs, immediate MIPS64, removed in Release 6 Doubleword Add Immediate
DADDIU rt, rs, immediate MIPS64 Doubleword Add Immediate Unsigned
DADD rd, rs, rt MIPS64 Doubleword Add
DADDU rd, rs, rt MIPS64 Doubleword Add Unsigned
DCLO rd, rs MIPS64 Count Leading Ones in Doubleword
DCLZ rd, rs MIPS64 Count Leading Zeros in Doubleword
DDIV rs, rt MIPS64, removed in Release 6 Doubleword Divide
DDIVU rs, rt MIPS64, removed in Release 6 Doubleword Divide Unsigned
DERET EJTAG Debug Exception Return
DEXTM rt, rs, pos, size MIPS64 Release 2 Doubleword Extract Bit Field Middle
DEXT rt, rs, pos, size MIPS64 Release 2 Doubleword Extract Bit Field
DEXTU rt, rs, pos, size MIPS64 Release 2 Doubleword Extract Bit Field Upper
DINSM rt, rs, pos, size MIPS64 Release 2 Doubleword Insert Bit Field Middle
DINS rt, rs, pos, size MIPS64 Release 2 Doubleword Insert Bit Field
DINSU rt, rs, pos, size MIPS64 Release 2 Doubleword Insert Bit Field Upper
DI rt MIPS32 Release 2 Disable Interrupts
DIV.S fd, fs, ft MIPS32 Floating Point Divide
DIV.D fd, fs, ft MIPS32 Floating Point Divide
DIV rd,rs,rt MIPS32 Release 6 Divide Words Signed
MOD rd,rs,rt MIPS32 Release 6 Modulo Words Signed
DIVU rd,rs,rt MIPS32 Release 6 Divide Words Unsigned
MODU rd,rs,rt MIPS32 Release 6 Modulo Words Unsigned
DDIV rd,rs,rt MIPS64 Release 6 Divide Doublewords Signed
DMOD rd,rs,rt MIPS64 Release 6 Modulo Doublewords Signed
DDIVU rd,rs,rt MIPS64 Release 6 Divide Doublewords Unsigned
DMODU rd,rs,rt MIPS64 Release 6 Modulo Doublewords Unsigned
DIV rs, rt MIPS32, removed in Release 6 Divide Word
DIVU rs, rt MIPS32, removed in Release 6 Divide Unsigned Word
DMFC0 rt, rd, sel MIPS64 Doubleword Move from Coprocessor 0
DMFC1 rt,fs MIPS64 Doubleword Move from Floating Point
DMFC2, rt, rd, sel MIPS64 Doubleword Move from Coprocessor 2
DMTC0 rt, rd, sel MIPS64 Doubleword Move to Coprocessor 0
DMTC1 rt, fs MIPS64 Doubleword Move to Floating Point
DMTC2 rt, Impl, sel MIPS64 Doubleword Move to Coprocessor 2
DMULT rs, rt MIPS64, removed in Release 6 Doubleword Multiply
DMULTU rs, rt MIPS64, removed in Release 6 Doubleword Multiply Unsigned
DROTR32 rd, rt, sa MIPS64 Release 2 Doubleword Rotate Right Plus 32
DROTR rd, rt, sa MIPS64 Release 2 Doubleword Rotate Right
DROTRV rd, rt, rs MIPS64 Release 2 Doubleword Rotate Right Variable
DSBH rd, rt MIPS64 Release 2 Doubleword Swap Bytes Within Halfwords
DSHD rd, rt MIPS64 Release 2 Doubleword Swap Halfwords Within Doublewords
DSLL32 rd, rt, sa MIPS64 Doubleword Shift Left Logical Plus 32
DSLL rd, rt, sa MIPS64 Doubleword Shift Left Logical
DSLLV rd, rt, rs MIPS64 Doubleword Shift Left Logical Variable
DSRA32 rd, rt, sa MIPS64 Doubleword Shift Right Arithmetic Plus 32
DSRA rd, rt, sa MIPS64 Doubleword Shift Right Arithmetic
DSRAV rd, rt, rs MIPS64 Doubleword Shift Right Arithmetic Variable
DSRL32 rd, rt, sa MIPS64 Doubleword Shift Right Logical Plus 32
DSRL rd, rt, sa MIPS64 Doubleword Shift Right Logical
DSRLV rd, rt, rs MIPS64 Doubleword Shift Right Logical Variable
DSUB rd, rs, rt MIPS64 Doubleword Subtract
DSUBU rd, rs, rt MIPS64 Doubleword Subtract Unsigned
DVP rt MIPS32 Release 6 Disable Virtual Processor
EHB Assembly Idiom MIPS32 Release 2 Execution Hazard Barrier
EI rt MIPS32 Release 2 Enable Interrupts
ERET MIPS32 Exception Return
ERETNC MIPS32 Release 5 Exception Return No Clear
EVP rt MIPS32 Release 6 Enable Virtual Processor
EXT rt, rs, pos, size MIPS32 Release 2 Extract Bit Field
FLOOR.L.S fd, fs MIPS64, MIPS32 Release 2 Floating Point Floor Convert to Long Fixed Point
FLOOR.L.D fd, fs MIPS64, MIPS32 Release 2 Floating Point Floor Convert to Long Fixed Point
FLOOR.W.S fd, fs MIPS32 Floating Point Floor Convert to Word Fixed Point
FLOOR.W.D fd, fs MIPS32 Floating Point Floor Convert to Word Fixed Point
GINVI rs MIPS32 Release 6 Global Invalidate Instruction Cache
GINVT rs, type MIPS32 Release 6 Global Invalidate TLB
INS rt, rs, pos, size MIPS32 Release 2 Insert Bit Field
JALR.HB rd, rs MIPS32 Release 2 Jump and Link Register with Hazard Barrier
JALR rd, rs MIPS32 Jump and Link Register
JAL target MIPS32 Jump and Link
JALX target MIPS32 with (microMIPS or MIPS16e), removed in Release 6 Jump and Link Exchange
JIALC rt, offset MIPS32 Release 6 Jump Indexed and Link, Compact
JIC rt, offset MIPS32 Release 6 Jump Indexed, Compact
JR.HB rs MIPS32 Release 2 Jump Register with Hazard Barrier
JR rs MIPS32 Jump Register
J target MIPS32 Jump
LBE rt, offset(base) MIPS32 Load Byte EVA
LB rt, offset(base) MIPS32 Load Byte
LBUE rt, offset(base) MIPS32 Load Byte Unsigned EVA
LBU rt, offset(base) MIPS32 Load Byte Unsigned
LDC1 ft, offset(base) MIPS32 Load Doubleword to Floating Point
LDC2 rt, offset(base) MIPS32 Load Doubleword to Coprocessor 2
LDL rt, offset(base) MIPS64, removed in Release 6 Load Doubleword Left
LDPC rs, offset MIPS64 Release 6 Load Doubleword PC-relative
LDR rt, offset(base) MIPS64, removed in Release 6 Load Doubleword Right
LDXC1 fd, index(base) MIPS64,MIPS32 Release 2, removed in Release 6 Load Doubleword Indexed to Floating Point
LHE rt, offset(base) MIPS32 Load Halfword EVA
LH rt, offset(base) MIPS32 Load Halfword
LHUE rt, offset(base) MIPS32 Load Halfword Unsigned EVA
LHU rt, offset(base) MIPS32 Load Halfword Unsigned
LLDP rt, rd, (base) MIPS64 Release 6 Load Linked DoubleWord Paired
LLD rt, offset(base) MIPS64 Load Linked Doubleword
LLE rt, offset(base) MIPS32 Load Linked Word EVA
LL rt, offset(base) MIPS32 Load Linked Word
LLWPE rt, rd, (base) MIPS32 Release 6 Load Linked Word Paired EVA
LLWP rt, rd, (base) MIPS32 Release 6 Load Linked Word Paired
LSA rd,rs,rt,sa MIPS32 Release 6 Load Scaled Address, Doubleword Load Scaled Address
DLSA rd,rs,rt,sa MIPS64 Release 6 Load Scaled Address, Doubleword Load Scaled Address
LUI rt, immediate MIPS32, Assembly Idiom Release 6 Load Upper Immediate
LUXC1 fd, index(base) MIPS64, MIPS32 Release 2, removed in Release 6 Load Doubleword Indexed Unaligned to Floating Point
LWC1 ft, offset(base) MIPS32 Load Word to Floating Point
LWC2 rt, offset(base) MIPS32 Load Word to Coprocessor 2
LWE rt, offset(base) MIPS32 Load Word EVA
LWLE rt, offset(base) MIPS32, removed in Release 6 Load Word Left EVA
LWL rt, offset(base) MIPS32, removed in Release 6 Load Word Left
LWPC rs, offset MIPS32 Release 6 Load Word PC-relative
LWRE rt, offset(base) MIPS32, removed in Release 6 Load Word Right EVA
LWR rt, offset(base) MIPS32, removed in Release 6 Load Word Right
LW rt, offset(base) MIPS32 Load Word
LWUPC rs, offset MIPS64 Release 6 Load Word Unsigned PC-relative
LWU rt, offset(base) MIPS64 Load Word Unsigned
LWXC1 fd, index(base) MIPS64, MIPS32 Release 2, removed in Release 6 Load Word Indexed to Floating Point
MADD.S fd, fr, fs, ft MIPS64, MIPS32 Release 2, removed in Release 6 Floating Point Multiply Add
MADD.D fd, fr, fs, ft MIPS64, MIPS32 Release 2, removed in Release 6 Floating Point Multiply Add
MADD.PS fd, fr, fs, ft MIPS64, MIPS32 Release 2, removed in Release 6 Floating Point Multiply Add
MADDF.S fd, fs, ft MIPS32 Release 6 Floating Point Fused Multiply Add, Floating Point Fused Multiply Subtract
MADDF.D fd, fs, ft MIPS32 Release 6 Floating Point Fused Multiply Add, Floating Point Fused Multiply Subtract
MSUBF.S fd, fs, ft MIPS32 Release 6 Floating Point Fused Multiply Add, Floating Point Fused Multiply Subtract
MSUBF.D fd, fs, ft MIPS32 Release 6 Floating Point Fused Multiply Add, Floating Point Fused Multiply Subtract
MADD rs, rt MIPS32, removed in Release 6 Multiply and Add Word to Hi, Lo
MADDU rs, rt MIPS32, removed in Release 6 Multiply and Add Unsigned Word to Hi,Lo
MAX.S fd,fs,ft MIPS32 Release 6 Scalar Floating-Point Max/Min/maxNumMag/minNumMag
MAX.D fd,fs,ft MIPS32 Release 6 Scalar Floating-Point Max/Min/maxNumMag/minNumMag
MAXA.S fd,fs,ft MIPS32 Release 6 Scalar Floating-Point Max/Min/maxNumMag/minNumMag
MAXA.D fd,fs,ft MIPS32 Release 6 Scalar Floating-Point Max/Min/maxNumMag/minNumMag
MIN.S fd,fs,ft MIPS32 Release 6 Scalar Floating-Point Max/Min/maxNumMag/minNumMag
MIN.D fd,fs,ft MIPS32 Release 6 Scalar Floating-Point Max/Min/maxNumMag/minNumMag
MINA.S fd,fs,ft MIPS32 Release 6 Scalar Floating-Point Max/Min/maxNumMag/minNumMag
MINA.D fd,fs,ft MIPS32 Release 6 Scalar Floating-Point Max/Min/maxNumMag/minNumMag
MFC0 rt, rd, sel MIPS32 Move from Coprocessor 0
MFC1 rt, fs MIPS32 Move Word From Floating Point
MFC2, rt, Impl, sel MIPS32 Move Word From Coprocessor 2
MFHC0 rt, rd, sel MIPS32 Release 5 Move from High Coprocessor 0
MFHC1 rt, fs MIPS32 Release 2 Move Word From High Half of Floating Point Register
MFHC2, rt, rd, sel MIPS32 Release 2 Move Word From High Half of Coprocessor 2 Register
MFHI rd MIPS32, removed in Release 6 Move From HI Register
MFLO rd MIPS32, removed in Release 6 Move From LO Register
MOV.S fd, fs MIPS32 Floating Point Move
MOV.D fd, fs MIPS32 Floating Point Move
MOV.PS fd, fs MIPS64, MIPS32 Release 2, removed in Release 6 Floating Point Move
MOVF.S fd, fs, cc MIPS32, removed in Release 6 Floating Point Move Conditional on Floating Point False
MOVF.D fd, fs, cc MIPS32, removed in Release 6 Floating Point Move Conditional on Floating Point False
MOVF.PS fd, fs, cc MIPS64 removed in Release 6 Floating Point Move Conditional on Floating Point False
MOVF rd, rs, cc MIPS32, removed in Release 6 Move Conditional on Floating Point False
MOVN.S fd, fs, rt MIPS32, removed in Release 6 Floating Point Move Conditional on Not Zero
MOVN.D fd, fs, rt MIPS32, removed in Release 6 Floating Point Move Conditional on Not Zero
MOVN.PS fd, fs, rt MIPS64, MIPS32 Release 2, removed in Release 6 Floating Point Move Conditional on Not Zero
MOVN rd, rs, rt MIPS32, removed in Release 6 Move Conditional on Not Zero
MOVT.S fd, fs, cc MIPS32, removed in Release 6 Floating Point Move Conditional on Floating Point True
MOVT.D fd, fs, cc MIPS32, removed in Release 6 Floating Point Move Conditional on Floating Point True
MOVT.PS fd, fs, cc MIPS64, MIPS32 Release 2, removed in Release 6 Floating Point Move Conditional on Floating Point True
MOVT rd, rs, cc MIPS32, removed in Release 6 Move Conditional on Floating Point True
MOVZ.S fd, fs, rt MIPS32, removed in Release 6 Floating Point Move Conditional on Zero
MOVZ.D fd, fs, rt MIPS32, removed in Release 6 Floating Point Move Conditional on Zero
MOVZ.PS fd, fs, rt MIPS64, MIPS32 Release 2, removed in Release 6 Floating Point Move Conditional on Zero
MOVZ rd, rs, rt MIPS32, removed in Release 6 Move Conditional on Zero
MSUB.S fd, fr, fs, ft MIPS64, MIPS32 Release 2, removed in Release 6 Floating Point Multiply Subtract
MSUB.D fd, fr, fs, ft MIPS64, MIPS32 Release 2, removed in Release 6 Floating Point Multiply Subtract
MSUB.PS fd, fr, fs, ft MIPS64, MIPS32 Release 2, removed in Release 6 Floating Point Multiply Subtract
MSUB rs, rt MIPS32, removed in Release 6 Multiply and Subtract Word to Hi, Lo
MSUBU rs, rt MIPS32, removed in Release 6 Multiply and Subtract Word to Hi,Lo
MTC0 rt, rd, sel MIPS32 Move to Coprocessor 0
MTC1 rt, fs MIPS32 Move Word to Floating Point
MTC2 rt, Impl, sel MIPS32 Move Word to Coprocessor 2
MTHC0 rt, rd, sel MIPS32 Release 5 Move to High Coprocessor 0
MTHC1 rt, fs MIPS32 Release 2 Move Word to High Half of Floating Point Register
MTHC2 rt, Impl, sel MIPS32 Release 2 Move Word to High Half of Coprocessor 2 Register
MTHI rs MIPS32, removed in Release 6 Move to HI Register
MTLO rs MIPS32, removed in Release 6 Move to LO Register
MUL.S fd, fs, ft MIPS32 Floating Point Multiply
MUL.D fd, fs, ft MIPS32 Floating Point Multiply
MUL.PS fd, fs, ft MIPS64, MIPS32 Release 3, removed in Release 6 Floating Point Multiply
MUL rd,rs,rt MIPS32 Release 6 Multiply Words Signed, Low Word
MUH rd,rs,rt MIPS32 Release 6 Multiply Words Signed, High Word
MULU rd,rs,rt MIPS32 Release 6 Multiply Words Unsigned, Low Word
MUHU rd,rs,rt MIPS32 Release 6 Multiply Words Unsigned, High Word
DMUL rd,rs,rt MIPS64 Release 6 Multiply Doublewords Signed, Low Doubleword
DMUH rd,rs,rt MIPS64 Release 6 Multiply Doublewords Signed, High Doubleword
DMULU rd,rs,rt MIPS64 Release 6 Multiply Doublewords Unsigned, Low Doubleword
DMUHU rd,rs,rt MIPS64 Release 6 Multiply Doublewords Unsigned, High Doubleword
MUL rd, rs, rt MIPS32, removed in Release 6 Multiply Word to GPR
MULT rs, rt MIPS32, removed in Release 6 Multiply Word
MULTU rs, rt MIPS32, removed in Release 6 Multiply Unsigned Word
NAL Assembly Idiom MIPS32 pre-Release 6, MIPS32 Release 6 No-op and Link
NEG.S fd, fs MIPS32 Floating Point Negate
NEG.D fd, fs MIPS32 Floating Point Negate
NEG.PS fd, fs MIPS64, MIPS32 Release 2, removed in Release 6 Floating Point Negate
NMADD.S fd, fr, fs, ft MIPS64, MIPS32 Release 2, removed in Release 6 Floating Point Negative Multiply Add
NMADD.D fd, fr, fs, ft MIPS64, MIPS32 Release 2, removed in Release 6 Floating Point Negative Multiply Add
NMADD.PS fd, fr, fs, ft MIPS64, MIPS32 Release 2, removed in Release 6 Floating Point Negative Multiply Add
NMSUB.S fd, fr, fs, ft MIPS64, MIPS32 Release 2, removed in Release 6 Floating Point Negative Multiply Subtract
NMSUB.D fd, fr, fs, ft MIPS64, MIPS32 Release 2, removed in Release 6 Floating Point Negative Multiply Subtract
NMSUB.PS fd, fr, fs, ft MIPS64, MIPS32 Release 2, removed in Release 6 Floating Point Negative Multiply Subtract
NOP Assembly Idiom No Operation
NOR rd, rs, rt MIPS32 Not Or
ORI rt, rs, immediate MIPS32 Or Immediate
OR rd, rs, rt MIPS32 Or
PAUSE MIPS32 Release 2/MT Module Wait for the LLBit to clear.
PLL.PS fd, fs, ft MIPS64, MIPS32 Release 2, removed in Release 6 Pair Lower Lower
PLU.PS fd, fs, ft MIPS64, MIPS32 Release 2, removed in Release 6 Pair Lower Upper
PREFE hint,offset(base) MIPS32 Prefetch EVA
PREF hint,offset(base) MIPS32 Prefetch
PREFX hint, index(base) MIPS64, MIPS32 Release 2, removed in Release 6 Prefetch Indexed
PUL.PS fd, fs, ft MIPS64, MIPS32 Release 2, removed in Release 6 Pair Upper Lower
PUU.PS fd, fs, ft MIPS64, MIPS32 Release 2,, removed in Release 6 Pair Upper Upper
RDHWR rt,rd,sel MIPS32 Release 2 Read Hardware Register
RDPGPR rd, rt MIPS32 Release 2 Read GPR from Previous Shadow Set
RECIP.S fd, fs MIPS64, MIPS32 Release 2 Reciprocal Approximation
RECIP.D fd, fs MIPS64, MIPS32 Release 2 Reciprocal Approximation
RINT.fmt MIPS32 Release 6 Floating-Point Round to Integral
RINT.S fd,fs MIPS32 Release 6 Floating-Point Round to Integral
RINT.D fd,fs MIPS32 Release 6 Floating-Point Round to Integral
ROTR rd, rt, sa SmartMIPS Crypto, MIPS32 Release 2 Rotate Word Right
ROTRV rd, rt, rs SmartMIPS Crypto, MIPS32 Release 2 Rotate Word Right Variable
ROUND.L.S fd, fs MIPS64, MIPS32 Release 2 Floating Point Round to Long Fixed Point
ROUND.L.D fd, fs MIPS64, MIPS32 Release 2 Floating Point Round to Long Fixed Point
ROUND.W.S fd, fs MIPS32 Floating Point Round to Word Fixed Point
ROUND.W.D fd, fs MIPS32 Floating Point Round to Word Fixed Point
RSQRT.S fd, fs MIPS64, MIPS32 Release 2 Reciprocal Square Root Approximation
RSQRT.D fd, fs MIPS64, MIPS32 Release 2 Reciprocal Square Root Approximation
SBE rt, offset(base) MIPS32 Store Byte EVA
SB rt, offset(base) MIPS32 Store Byte
SCDP rt, rd, (base) MIPS32 Release 6 Store Conditional DoubleWord Paired
SCD rt, offset(base) MIPS64 Store Conditional Doubleword
SCE rt, offset(base) MIPS32 Store Conditional Word EVA
SC rt, offset(base) MIPS32 Store Conditional Word
SCWPE rt, rd, (base) MIPS32 Release 6 Store Conditional Word Paired EVA
SCWP rt, rd, (base) MIPS32 Release 6 Store Conditional Word Paired
SDBBP code EJTAG Software Debug Breakpoint
SDC1 ft, offset(base) MIPS32 Store Doubleword from Floating Point
SDC2 rt, offset(base) MIPS32 Store Doubleword from Coprocessor 2
SDL rt, offset(base) MIPS64, removed in Release 6 Store Doubleword Left
SDR rt, offset(base) MIPS64, removed in Release 6 Store Doubleword Right
SD rt, offset(base) MIPS64 Store Doubleword
SDXC1 fs, index(base) MIPS64, MIPS32 Release 2, removed in Release 6 Store Doubleword Indexed from Floating Point
SEB rd, rt MIPS32 Release 2 Sign-Extend Byte
SEH rd, rt MIPS32 Release 2 Sign-Extend Halfword
SEL.S fd,fs,ft MIPS32 Release 6 Select floating point values with FPR condition
SEL.D fd,fs,ft MIPS32 Release 6 Select floating point values with FPR condition
SELEQZ.S fd,fs,ft MIPS32 Release 6 Select floating point value or zero with FPR condition.
SELEQZ.D fd,fs,ft MIPS32 Release 6 Select floating point value or zero with FPR condition.
SELNEZ.S fd,fs,ft MIPS32 Release 6 Select floating point value or zero with FPR condition.
SELNEZ.D fd,fs,ft MIPS32 Release 6 Select floating point value or zero with FPR condition.
SELEQZ rd,rs,rt MIPS32 Release 6 Select integer GPR value or zero
SELNEZ rd,rs,rt MIPS32 Release 6 Select integer GPR value or zero
SHE rt, offset(base) MIPS32 Store Halfword EVA
SH rt, offset(base) MIPS32 Store Halfword
SIGRIE code MIPS32 Release 6 Signal Reserved Instruction Exception
SLL rd, rt, sa MIPS32 Shift Word Left Logical
SLLV rd, rt, rs MIPS32 Shift Word Left Logical Variable
SLTI rt, rs, immediate MIPS32 Set on Less Than Immediate
SLTIU rt, rs, immediate MIPS32 Set on Less Than Immediate Unsigned
SLT rd, rs, rt MIPS32 Set on Less Than
SLTU rd, rs, rt MIPS32 Set on Less Than Unsigned
SQRT.S fd, fs MIPS32 Floating Point Square Root
SQRT.D fd, fs MIPS32 Floating Point Square Root
SRA rd, rt, sa MIPS32 Shift Word Right Arithmetic
SRAV rd, rt, rs MIPS32 Shift Word Right Arithmetic Variable
SRL rd, rt, sa MIPS32 Shift Word Right Logical
SRLV rd, rt, rs MIPS32 Shift Word Right Logical Variable
SSNOP Assembly Idiom MIPS32 Superscalar No Operation
SUB.S fd, fs, ft MIPS32 Floating Point Subtract
SUB.D fd, fs, ft MIPS32 Floating Point Subtract
SUB.PS fd, fs, ft MIPS64, MIPS32 Release 2, removed in Release 6 Floating Point Subtract
SUB rd, rs, rt MIPS32 Subtract Word
SUBU rd, rs, rt MIPS32 Subtract Unsigned Word
SUXC1 fs, index(base) MIPS64, MIPS32 Release 2, removed in Release 6 Store Doubleword Indexed Unaligned from Floating Point
SWC1 ft, offset(base) MIPS32 Store Word from Floating Point
SWC2 rt, offset(base) MIPS32 Store Word from Coprocessor 2
SWE rt, offset(base) MIPS32 Store Word EVA
SWLE rt, offset(base) MIPS32, removed in Release 6 Store Word Left EVA
SWL rt, offset(base) MIPS32, removed in Release 6 Store Word Left
SWRE rt, offset(base) MIPS32, removed in Release 6 Store Word Right EVA
SWR rt, offset(base) MIPS32, removed in Release 6 Store Word Right
SW rt, offset(base) MIPS32 Store Word
SWXC1 fs, index(base) MIPS64, MIPS32 Release 2, removed in Release 6 Store Word Indexed from Floating Point
SYNCI offset(base) MIPS32 Release 2 Synchronize Caches to Make Instruction Writes Effective
SYNC stype MIPS32 Synchronize Shared Memory
SYSCALL MIPS32 System Call
TEQI rs, immediate MIPS32, removed in Release 6 Trap if Equal Immediate
TEQ rs, rt MIPS32 Trap if Equal
TGEI rs, immediate MIPS32, removed in Release 6 Trap if Greater or Equal Immediate
TGEIU rs, immediate MIPS32, removed in Release 6 Trap if Greater or Equal Immediate Unsigned
TGE rs, rt MIPS32 Trap if Greater or Equal
TGEU rs, rt MIPS32 Trap if Greater or Equal Unsigned
TLBINV MIPS32 TLB Invalidate
TLBINVF MIPS32 TLB Invalidate Flush
TLBP MIPS32 Probe TLB for Matching Entry
TLBR MIPS32 Read Indexed TLB Entry
TLBWI MIPS32 Write Indexed TLB Entry
TLBWR MIPS32 Write Random TLB Entry
TLTI rs, immediate MIPS32, removed in Release 6 Trap if Less Than Immediate
TLTIU rs, immediate MIPS32, removed in Release 6 Trap if Less Than Immediate Unsigned
TLT rs, rt MIPS32 Trap if Less Than
TLTU rs, rt MIPS32 Trap if Less Than Unsigned
TNEI rs, immediate MIPS32, removed in Release 6 Trap if Not Equal Immediate
TNE rs, rt MIPS32 Trap if Not Equal
TRUNC.L.S fd, fs MIPS64, MIPS32 Release 2 Floating Point Truncate to Long Fixed Point
TRUNC.L.D fd, fs MIPS64, MIPS32 Release 2 Floating Point Truncate to Long Fixed Point
TRUNC.W.S fd, fs MIPS32 Floating Point Truncate to Word Fixed Point
TRUNC.W.D fd, fs MIPS32 Floating Point Truncate to Word Fixed Point
WAIT MIPS32 Enter Standby Mode
WRPGPR rd, rt MIPS32 Release 2 Write to GPR in Previous Shadow Set
WSBH rd, rt MIPS32 Release 2 Word Swap Bytes Within Halfwords
XORI rt, rs, immediate MIPS32 Exclusive OR Immediate
XOR rd, rs, rt MIPS32 Exclusive OR

MIPS ASE-3D ISA Reference

MD00099-2B-MIPS3D64-AFP-02.61

ADDR.PS fd, fs, ft MIPS-3D Floating Point Reduction Add
BC1ANY2F cc,offset MIPS-3D Branch on Any of Two Floating Point Condition Codes False
BC1ANY2T cc,offset MIPS-3D Branch on Any of Two Floating Point Condition Codes True
BC1ANY4F cc,offset MIPS-3D Branch on Any of Four Floating Point Condition Codes False
BC1ANY4T cc,offset MIPS-3D Branch on Any of Four Floating Point Condition Codes True
CABS.cond.S cc,fs,ft MIPS-3D Floating Point Absolute Compare
CABS.cond.D cc,fs,ft MIPS-3D Floating Point Absolute Compare
CABS.cond.PS cc,fs,ft MIPS-3D Floating Point Absolute Compare
CVT.PS.PW fd,fs MIPS-3D Floating Point Convert Paired Word to Paired Single
CVT.PW.PS fd,fs MIPS-3D Floating Point Convert Paired Single to Paired Word
MULR.PS fd, fs, ft MIPS-3D Floating Point Reduction Multiply
RECIP1.S fd,fs MIPS-3D Floating Point Reduced Precision Reciprocal (Sequence Step 1)
RECIP1.D fd,fs MIPS-3D Floating Point Reduced Precision Reciprocal (Sequence Step 1)
RECIP1.PS fd,fs MIPS-3D Floating Point Reduced Precision Reciprocal (Sequence Step 1)
RECIP2.S fd,fs,ft MIPS-3D Floating Point Reduced Precision Reciprocal (Sequence Step 2)
RECIP2.D fd,fs,ft MIPS-3D Floating Point Reduced Precision Reciprocal (Sequence Step 2)
RECIP2.PS fd,fs,ft MIPS-3D Floating Point Reduced Precision Reciprocal (Sequence Step 2)
RSQRT1.S fd, fs MIPS-3D Floating Point Reduced Precision Reciprocal Square Root (Sequence Step 1)
RSQRT1.D fd, fs MIPS-3D Floating Point Reduced Precision Reciprocal Square Root (Sequence Step 1)
RSQRT1.PS fd, fs MIPS-3D Floating Point Reduced Precision Reciprocal Square Root (Sequence Step 1)
RSQRT2.S fd, fs, ft MIPS-3D Floating Point Reduced Precision Reciprocal Square Root (Sequence Step 2)
RSQRT2.D fd, fs, ft MIPS-3D Floating Point Reduced Precision Reciprocal Square Root (Sequence Step 2)
RSQRT2.PS fd, fs, ft MIPS-3D Floating Point Reduced Precision Reciprocal Square Root (Sequence Step 2)

MIPS ASE-DSP ISA Reference

MD00375-2B-MIPS64DSP-AFP-03.02

ABSQ_S.PH rd, rt MIPSDSP Find Absolute Value of Two Fractional Halfwords
ABSQ_S.QB rd, rt MIPSDSP-R2 Find Absolute Value of Four Fractional Byte Values
ABSQ_S.W rd, rt MIPSDSP Find Absolute Value of Fractional Word
ADDQH.PH rd, rs, rt MIPSDSP-R2 Add Fractional Halfword Vectors And Shift Right to Halve Results
ADDQH_R.PH rd, rs, rt MIPSDSP-R2 Add Fractional Halfword Vectors And Shift Right to Halve Results
ADDQH.W rd, rs, rt MIPSDSP-R2 Add Fractional Words And Shift Right to Halve Results
ADDQH_R.W rd, rs, rt MIPSDSP-R2 Add Fractional Words And Shift Right to Halve Results
ADDQ.PH rd, rs, rt MIPSDSP Add Fractional Halfword Vectors
ADDQ_S.PH rd, rs, rt MIPSDSP Add Fractional Halfword Vectors
ADDQ_S.W rd, rs, rt MIPSDSP Add Fractional Words
ADDSC rd, rs, rt MIPSDSP Add Signed Word and Set Carry Bit
ADDUH.QB rd, rs, rt MIPSDSP-R2 Unsigned Add Vector Quad-Bytes And Right Shift to Halve Results
ADDUH_R.QB rd, rs, rt MIPSDSP-R2 Unsigned Add Vector Quad-Bytes And Right Shift to Halve Results
ADDU.PH rd, rs, rt MIPSDSP-R2 Unsigned Add Integer Halfwords
ADDU_S.PH rd, rs, rt MIPSDSP-R2 Unsigned Add Integer Halfwords
ADDU.QB rd, rs, rt MIPSDSP Unsigned Add Quad Byte Vectors
ADDU_S.QB rd, rs, rt MIPSDSP Unsigned Add Quad Byte Vectors
ADDWC rd, rs, rt MIPSDSP Add Word with Carry Bit
APPEND rt, rs, sa MIPSDSP-R2 Left Shift and Append Bits to the LSB
BALIGN rt, rs, bp MIPSDSP-R2 Byte Align Contents from Two Registers
BITREV rd, rt MIPSDSP Bit-Reverse Halfword
BPOSGE32C offset MIPSDSP-R3 Branch on Greater Than or Equal To Value 32 inDSPControl Pos Field
BPOSGE32 offset MIPSDSP Branch on Greater Than or Equal To Value 32 inDSPControl Pos Field
CMP.EQ.PH rs, rt MIPSDSP Compare Vectors of Signed Integer Halfword Values
CMP.LT.PH rs, rt MIPSDSP Compare Vectors of Signed Integer Halfword Values
CMP.LE.PH rs, rt MIPSDSP Compare Vectors of Signed Integer Halfword Values
CMPGDU.EQ.QB rd, rs, rt MIPSDSP-R2 Compare Unsigned Vector of Four Bytes and Write Result to GPR and DSPControl
CMPGDU.LT.QB rd, rs, rt MIPSDSP-R2 Compare Unsigned Vector of Four Bytes and Write Result to GPR and DSPControl
CMPGDU.LE.QB rd, rs, rt MIPSDSP-R2 Compare Unsigned Vector of Four Bytes and Write Result to GPR and DSPControl
CMPGU.EQ.QB rd, rs, rt MIPSDSP Compare Vectors of Unsigned Byte Values and Write Results to a GPR
CMPGU.LT.QB rd, rs, rt MIPSDSP Compare Vectors of Unsigned Byte Values and Write Results to a GPR
CMPGU.LE.QB rd, rs, rt MIPSDSP Compare Vectors of Unsigned Byte Values and Write Results to a GPR
CMPU.EQ.QB rs, rt MIPSDSP Compare Vectors of Unsigned Byte Values
CMPU.LT.QB rs, rt MIPSDSP Compare Vectors of Unsigned Byte Values
CMPU.LE.QB rs, rt MIPSDSP Compare Vectors of Unsigned Byte Values
DPA.W.PH ac, rs, rt MIPSDSP-R2 Dot Product with Accumulate on Vector Integer Halfword Elements
DPAQX_S.W.PH ac, rs, rt MIPSDSP-R2 Cross Dot Product with Accumulation on Fractional Halfword Elements
DPAQX_SA.W.PH ac, rs, rt MIPSDSP-R2 Cross Dot Product with Accumulation on Fractional Halfword Elements
DPAQ_S.W.PH ac, rs, rt MIPSDSP Dot Product with Accumulation on Fractional Halfword Elements
DPAQ_SA.L.W ac, rs, rt MIPSDSP Dot Product with Accumulate on Fractional Word Element
DPAU.H.QBL ac, rs, rt MIPSDSP Dot Product with Accumulate on Vector Unsigned Byte Elements
DPAU.H.QBR ac, rs, rt MIPSDSP Dot Product with Accumulate on Vector Unsigned Byte Elements
DPAX.W.PH ac, rs, rt MIPSDSP-R2 Cross Dot Product with Accumulate on Vector Integer Halfword Elements
DPS.W.PH ac, rs, rt MIPSDSP-R2 Dot Product with Subtract on Vector Integer Half-Word Elements
DPSQX_S.W.PH ac, rs, rt MIPSDSP-R2 Cross Dot Product with Subtraction on Fractional Halfword Elements
DPSQX_SA.W.PH ac, rs, rt MIPSDSP-R2 Cross Dot Product with Subtraction on Fractional Halfword Elements
DPSQ_S.W.PH ac, rs, rt MIPSDSP Dot Product with Subtraction on Fractional Halfword Elements
DPSQ_SA.L.W ac, rs, rt MIPSDSP Dot Product with Subtraction on Fractional Word Element
DPSU.H.QBL ac, rs, rt MIPSDSP Dot Product with Subtraction on Vector Unsigned Byte Elements
DPSU.H.QBR ac, rs, rt MIPSDSP Dot Product with Subtraction on Vector Unsigned Byte Elements
DPSX.W.PH ac, rs, rt MIPSDSP-R2 Cross Dot Product with Subtract on Vector Integer Halfword Elements
EXTPDP rt, ac, size MIPSDSP Extract Fixed Bitfield From Arbitrary Position in Accumulator to GPR and Decrement Pos
EXTPDPV rt, ac, rs MIPSDSP Extract Variable Bitfield From Arbitrary Position in Accumulator to GPR and Decrement Pos
EXTP rt, ac, size MIPSDSP Extract Fixed Bitfield From Arbitrary Position in Accumulator to GPR
EXTPV rt, ac, rs MIPSDSP Extract Variable Bitfield From Arbitrary Position in Accumulator to GPR
EXTRV.W rt, ac, rs MIPSDSP Extract Word Value With Variable Right Shift From Accumulator to GPR
EXTRV_R.W rt, ac, rs MIPSDSP Extract Word Value With Variable Right Shift From Accumulator to GPR
EXTRV_RS.W rt, ac, rs MIPSDSP Extract Word Value With Variable Right Shift From Accumulator to GPR
EXTRV_S.H rt, ac, rs MIPSDSP Extract Halfword Value Variable From Accumulator to GPR With Right Shift and Saturate
EXTR.W rt, ac, shift MIPSDSP Extract Word Value With Right Shift From Accumulator to GPR
EXTR_R.W rt, ac, shift MIPSDSP Extract Word Value With Right Shift From Accumulator to GPR
EXTR_RS.W rt, ac, shift MIPSDSP Extract Word Value With Right Shift From Accumulator to GPR
EXTR_S.H rt, ac, shift MIPSDSP Extract Halfword Value From Accumulator to GPR With Right Shift and Saturate
INSV rt, rs MIPSDSP Insert Bit Field Variable
LBUX rd, index(base) MIPSDSP Load Unsigned Byte Indexed
LDX rd, index(base) MIPSDSP Load Doubleword Indexed
LHX rd, index(base) MIPSDSP Load Halfword Indexed
LWX rd, index(base) MIPSDSP Load Word Indexed
MADD ac, rs, rt MIPS32 pre-Release 6, MIPSDSP Multiply Word and Add to Accumulator
MADDU ac, rs, rt MIPS32 pre-Release 6, MIPSDSP Multiply Unsigned Word and Add to Accumulator
MAQ_S.W.PHL ac, rs, rt MIPSDSP Multiply with Accumulate Single Vector Fractional Halfword Element
MAQ_SA.W.PHL ac, rs, rt MIPSDSP Multiply with Accumulate Single Vector Fractional Halfword Element
MAQ_S.W.PHR ac, rs, rt MIPSDSP Multiply with Accumulate Single Vector Fractional Halfword Element
MAQ_SA.W.PHR ac, rs, rt MIPSDSP Multiply with Accumulate Single Vector Fractional Halfword Element
MFHI rd, ac MIPS32 pre-Release 6, MIPSDSP Move from HI register
MFLO rd, ac MIPS32 pre-Release 6, MIPSDSP Move from LO register
MODSUB rd, rs, rt MIPSDSP Modular Subtraction on an Index Value
MSUB ac, rs, rt MIPS32 pre-Release 6, MIPSDSP Multiply Word and Subtract from Accumulator
MSUBU ac, rs, rt MIPS32 pre-Release 6, MIPSDSP Multiply Unsigned Word and Add to Accumulator
MTHI rs, ac MIPS32 pre-Release 6, MIPSDSP Move to HI register
MTHLIP rs, ac MIPSDSP Copy LO to HI and a GPR to LO and Increment Pos by 32
MTLO rs, ac MIPS32 pre-Release 6, MIPSDSP Move to LO register
MULEQ_S.W.PHL rd, rs, rt MIPSDSP Multiply Vector Fractional Left Halfwords to Expanded Width Products
MULEQ_S.W.PHR rd, rs, rt MIPSDSP Multiply Vector Fractional Right Halfwords to Expanded Width Products
MULEU_S.PH.QBL rd, rs, rt MIPSDSP Multiply Unsigned Vector Left Bytes by Halfwords to Halfword Products
MULEU_S.PH.QBR rd, rs, rt MIPSDSP Multiply Unsigned Vector Right Bytes with halfwords to Half Word Products
MULQ_RS.PH rd, rs, rt MIPSDSP Multiply Vector Fractional Halfwords to Fractional Halfword Products
MULQ_RS.W rd, rs, rt MIPSDSP-R2 Multiply Fractional Words to Same Size Product with Saturation and Rounding
MULQ_S.PH rd, rs, rt MIPSDSP-R2 Multiply Vector Fractional Half-Words to Same Size Products
MULQ_S.W rd, rs, rt MIPSDSP-R2 Multiply Fractional Words to Same Size Product with Saturation
MULSA.W.PH ac, rs, rt MIPSDSP-R2 Multiply and Subtract Vector Integer Halfword Elements and Accumulate
MULSAQ_S.W.PH ac, rs, rt MIPSDSP Multiply And Subtract Vector Fractional Halfwords And Accumulate
MULT ac, rs, rt MIPS32 pre-Release 6, MIPSDSP Multiply Word
MULTU ac, rs, rt MIPS32 pre-Release 6, MIPSDSP Multiply Unsigned Word
MUL.PH rd, rs, rt MIPSDSP-R2 Multiply Vector Integer HalfWords to Same Size Products
MUL_S.PH rd, rs, rt MIPSDSP-R2 Multiply Vector Integer HalfWords to Same Size Products
PACKRL.PH rd, rs, rt MIPSDSP Pack a Vector of Halfwords from Vector Halfword Sources
PICK.PH rd, rs, rt MIPSDSP Pick a Vector of Halfword Values Based on Condition Code Bits
PICK.QB rd, rs, rt MIPSDSP Pick a Vector of Byte Values Based on Condition Code Bits
PRECEQ.W.PHL rd, rt MIPSDSP Precision Expand Fractional Halfword to Fractional Word Value
PRECEQ.W.PHR rd, rt MIPSDSP Precision Expand Fractional Halfword to Fractional Word Value
PRECEQU.PH.QBLA rd, rt MIPSDSP Precision Expand two Unsigned Bytes to Fractional Halfword Values
PRECEQU.PH.QBL rd, rt MIPSDSP Precision Expand two Unsigned Bytes to Fractional Halfword Values
PRECEQU.PH.QBRA rd, rt MIPSDSP Precision Expand two Unsigned Bytes to Fractional Halfword Values
PRECEQU.PH.QBR rd, rt MIPSDSP Precision Expand two Unsigned Bytes to Fractional Halfword Values
PRECEU.PH.QBLA rd, rt MIPSDSP Precision Expand Two Unsigned Bytes to Unsigned Halfword Values
PRECEU.PH.QBL rd, rt MIPSDSP Precision Expand Two Unsigned Bytes to Unsigned Halfword Values
PRECEU.PH.QBRA rd, rt MIPSDSP Precision Expand Two Unsigned Bytes to Unsigned Halfword Values
PRECEU.PH.QBR rd, rt MIPSDSP Precision Expand two Unsigned Bytes to Unsigned Halfword Values
PRECR.QB.PH rd, rs, rt MIPSDSP-R2 Precision Reduce Four Integer Halfwords to Four Bytes
PRECRQ.PH.W rd, rs, rt MIPSDSP Precision Reduce Fractional Words to Fractional Halfwords
PRECRQ.QB.PH rd, rs, rt MIPSDSP Precision Reduce Four Fractional Halfwords to Four Bytes
PRECRQU_S.QB.PH rd, rs, rt MIPSDSP Precision Reduce Fractional Halfwords to Unsigned Bytes With Saturation
PRECRQ_RS.PH.W rd, rs, rt MIPSDSP Precision Reduce Fractional Words to Halfwords With Rounding and Saturation
PRECR_SRA.PH.W rt, rs, sa MIPSDSP-R2 Precision Reduce Two Integer Words to Halfwords after a Right Shift
PRECR_SRA_R.PH.W rt, rs, sa MIPSDSP-R2 Precision Reduce Two Integer Words to Halfwords after a Right Shift
PREPEND rt, rs, sa MIPSDSP-R2 Right Shift and Prepend Bits to the MSB
RADDU.W.QB rd, rs MIPSDSP Unsigned Reduction Add Vector Quad Bytes
RDDSP rd, mask MIPSDSP Read DSPControl Register Fields to a GPR
REPL.PH rd, immediate MIPSDSP Replicate Immediate Integer into all Vector Element Positions
REPL.QB rd, immediate MIPSDSP Replicate Immediate Integer into all Vector Element Positions
REPLV.PH rd, rt MIPSDSP Replicate a Halfword into all Vector Element Positions
REPLV.QB rd, rt MIPSDSP Replicate Byte into all Vector Element Positions
SHILO ac, shift MIPSDSP Shift an Accumulator Value Leaving the Result in the Same Accumulator
SHILOV ac, rs MIPSDSP Variable Shift of Accumulator Value Leaving the Result in the Same Accumulator
SHLL.QB rd, rt, sa MIPSDSP Shift Left Logical Vector Quad Bytes
SHLLV.QB rd, rt, rs MIPSDSP Shift Left Logical Variable Vector Quad Bytes
SHLLV.PH rd, rt, rs MIPSDSP Shift Left Logical Variable Vector Pair Halfwords
SHLLV_S.PH rd, rt, rs MIPSDSP Shift Left Logical Variable Vector Pair Halfwords
SHLLV_S.W rd, rt, rs MIPSDSP Shift Left Logical Variable Vector Word
SHLL.PH rd, rt, sa MIPSDSP Shift Left Logical Vector Pair Halfwords
SHLL_S.PH rd, rt, sa MIPSDSP Shift Left Logical Vector Pair Halfwords
SHLL_S.W rd, rt, sa MIPSDSP Shift Left Logical Word with Saturation
SHRAV.PH rd, rt, rs MIPSDSP Shift Right Arithmetic Variable Vector Pair Halfwords
SHRAV_R.PH rd, rt, rs MIPSDSP Shift Right Arithmetic Variable Vector Pair Halfwords
SHRAV.QB rd, rt, rs MIPSDSP-R2 Shift Right Arithmetic Variable Vector of Four Bytes
SHRAV_R.QB rd, rt, rs MIPSDSP-R2 Shift Right Arithmetic Variable Vector of Four Bytes
SHRAV_R.W rd, rt, rs MIPSDSP Shift Right Arithmetic Variable Word with Rounding
SHRA.PH rd, rt, sa MIPSDSP Shift Right Arithmetic Vector Pair Halfwords
SHRA_R.PH rd, rt, sa MIPSDSP Shift Right Arithmetic Vector Pair Halfwords
SHRA.QB rd, rt, sa MIPSDSP-R2 Shift Right Arithmetic Vector of Four Bytes
SHRA_R.QB rd, rt, sa MIPSDSP-R2 Shift Right Arithmetic Vector of Four Bytes
SHRA_R.W rd, rt, sa MIPSDSP Shift Right Arithmetic Word with Rounding
SHRL.PH rd, rt, sa MIPSDSP-R2 Shift Right Logical Two Halfwords
SHRL.QB rd, rt, sa MIPSDSP Shift Right Logical Vector Quad Bytes
SHRLV.PH rd, rt, rs MIPSDSP-R2 Shift Variable Right Logical Pair of Halfwords
SHRLV.QB rd, rt, rs MIPSDSP Shift Right Logical Variable Vector Quad Bytes
SUBQH.PH rd, rs, rt MIPSDSP-R2 Subtract Fractional Halfword Vectors And Shift Right to Halve Results
SUBQH_R.PH rd, rs, rt MIPSDSP-R2 Subtract Fractional Halfword Vectors And Shift Right to Halve Results
SUBQH.W rd, rs, rt MIPSDSP-R2 Subtract Fractional Words And Shift Right to Halve Results
SUBQH_R.W rd, rs, rt MIPSDSP-R2 Subtract Fractional Words And Shift Right to Halve Results
SUBQ.PH rd, rs, rt MIPSDSP Subtract Fractional Halfword Vector
SUBQ_S.PH rd, rs, rt MIPSDSP Subtract Fractional Halfword Vector
SUBQ_S.W rd, rs, rt MIPSDSP Subtract Fractional Word
SUBUH.QB rd, rs, rt MIPSDSP-R2 Subtract Unsigned Bytes And Right Shift to Halve Results
SUBUH_R.QB rd, rs, rt MIPSDSP-R2 Subtract Unsigned Bytes And Right Shift to Halve Results
SUBU.PH rd, rs, rt MIPSDSP-R2 Subtract Unsigned Integer Halfwords
SUBU_S.PH rd, rs, rt MIPSDSP-R2 Subtract Unsigned Integer Halfwords
SUBU.QB rd, rs, rt MIPSDSP Subtract Unsigned Quad Byte Vector
SUBU_S.QB rd, rs, rt MIPSDSP Subtract Unsigned Quad Byte Vector
WRDSP rs, mask MIPSDSP Write Fields to DSPControl Register from a GPR

MIPS ASE-MCU ISA Reference

MD00834-2B-MUCON-AFP-01.03

ACLR bit, offset(base) MIPS32, MCU ASE Atomically Clear Bit within Byte
ASET bit, offset(base) MIPS32, MCU ASE Atomically Set Bit within Byte
IRET MIPS32, MCU ASE Interrupt Return with automated interrupt epilogue handling

MIPS ASE-MSA ISA Reference

MD00868-1D-MSA64-AFP-01.12

ADDS_A.B wd,ws,wt MSA Vector Saturated Add of Absolute Values
ADDS_A.H wd,ws,wt MSA Vector Saturated Add of Absolute Values
ADDS_A.W wd,ws,wt MSA Vector Saturated Add of Absolute Values
ADDS_A.D wd,ws,wt MSA Vector Saturated Add of Absolute Values
ADDS_S.B wd,ws,wt MSA Vector Signed Saturated Add of Signed Values
ADDS_S.H wd,ws,wt MSA Vector Signed Saturated Add of Signed Values
ADDS_S.W wd,ws,wt MSA Vector Signed Saturated Add of Signed Values
ADDS_S.D wd,ws,wt MSA Vector Signed Saturated Add of Signed Values
ADDS_U.B wd,ws,wt MSA Vector Unsigned Saturated Add of Unsigned Values
ADDS_U.H wd,ws,wt MSA Vector Unsigned Saturated Add of Unsigned Values
ADDS_U.W wd,ws,wt MSA Vector Unsigned Saturated Add of Unsigned Values
ADDS_U.D wd,ws,wt MSA Vector Unsigned Saturated Add of Unsigned Values
ADDV.B wd,ws,wt MSA Vector Add
ADDV.H wd,ws,wt MSA Vector Add
ADDV.W wd,ws,wt MSA Vector Add
ADDV.D wd,ws,wt MSA Vector Add
ADDVI.B wd,ws,u5 MSA Immediate Add
ADDVI.H wd,ws,u5 MSA Immediate Add
ADDVI.W wd,ws,u5 MSA Immediate Add
ADDVI.D wd,ws,u5 MSA Immediate Add
ADD_A.B wd,ws,wt MSA Vector Add Absolute Values
ADD_A.H wd,ws,wt MSA Vector Add Absolute Values
ADD_A.W wd,ws,wt MSA Vector Add Absolute Values
ADD_A.D wd,ws,wt MSA Vector Add Absolute Values
AND.V wd,ws,wt MSA Vector Logical And
ANDI.B wd,ws,i8 MSA Immediate Logical And
ASUB_S.B wd,ws,wt MSA Vector Absolute Values of Signed Subtract
ASUB_S.H wd,ws,wt MSA Vector Absolute Values of Signed Subtract
ASUB_S.W wd,ws,wt MSA Vector Absolute Values of Signed Subtract
ASUB_S.D wd,ws,wt MSA Vector Absolute Values of Signed Subtract
ASUB_U.B wd,ws,wt MSA Vector Absolute Values of Unsigned Subtract
ASUB_U.H wd,ws,wt MSA Vector Absolute Values of Unsigned Subtract
ASUB_U.W wd,ws,wt MSA Vector Absolute Values of Unsigned Subtract
ASUB_U.D wd,ws,wt MSA Vector Absolute Values of Unsigned Subtract
AVER_S.B wd,ws,wt MSA Vector Signed Average Rounded
AVER_S.H wd,ws,wt MSA Vector Signed Average Rounded
AVER_S.W wd,ws,wt MSA Vector Signed Average Rounded
AVER_S.D wd,ws,wt MSA Vector Signed Average Rounded
AVER_U.B wd,ws,wt MSA Vector Unsigned Average Rounded
AVER_U.H wd,ws,wt MSA Vector Unsigned Average Rounded
AVER_U.W wd,ws,wt MSA Vector Unsigned Average Rounded
AVER_U.D wd,ws,wt MSA Vector Unsigned Average Rounded
AVE_S.B wd,ws,wt MSA Vector Signed Average
AVE_S.H wd,ws,wt MSA Vector Signed Average
AVE_S.W wd,ws,wt MSA Vector Signed Average
AVE_S.D wd,ws,wt MSA Vector Signed Average
AVE_U.B wd,ws,wt MSA Vector Unsigned Average
AVE_U.H wd,ws,wt MSA Vector Unsigned Average
AVE_U.W wd,ws,wt MSA Vector Unsigned Average
AVE_U.D wd,ws,wt MSA Vector Unsigned Average
BCLR.B wd,ws,wt MSA Vector Bit Clear
BCLR.H wd,ws,wt MSA Vector Bit Clear
BCLR.W wd,ws,wt MSA Vector Bit Clear
BCLR.D wd,ws,wt MSA Vector Bit Clear
BCLRI.B wd,ws,m MSA Immediate Bit Clear
BCLRI.H wd,ws,m MSA Immediate Bit Clear
BCLRI.W wd,ws,m MSA Immediate Bit Clear
BCLRI.D wd,ws,m MSA Immediate Bit Clear
BINSL.B wd,ws,wt MSA Vector Bit Insert Left
BINSL.H wd,ws,wt MSA Vector Bit Insert Left
BINSL.W wd,ws,wt MSA Vector Bit Insert Left
BINSL.D wd,ws,wt MSA Vector Bit Insert Left
BINSLI.B wd,ws,m MSA Immediate Bit Insert Left
BINSLI.H wd,ws,m MSA Immediate Bit Insert Left
BINSLI.W wd,ws,m MSA Immediate Bit Insert Left
BINSLI.D wd,ws,m MSA Immediate Bit Insert Left
BINSR.B wd,ws,wt MSA Vector Bit Insert Right
BINSR.H wd,ws,wt MSA Vector Bit Insert Right
BINSR.W wd,ws,wt MSA Vector Bit Insert Right
BINSR.D wd,ws,wt MSA Vector Bit Insert Right
BINSRI.B wd,ws,m MSA Immediate Bit Insert Right
BINSRI.H wd,ws,m MSA Immediate Bit Insert Right
BINSRI.W wd,ws,m MSA Immediate Bit Insert Right
BINSRI.D wd,ws,m MSA Immediate Bit Insert Right
BMNZ.V wd,ws,wt MSA Vector Bit Move If Not Zero
BMNZI.B wd,ws,i8 MSA Immediate Bit Move If Not Zero
BMZ.V wd,ws,wt MSA Vector Bit Move If Zero
BMZI.B wd,ws,i8 MSA Immediate Bit Move If Zero
BNEG.B wd,ws,wt MSA Vector Bit Negate
BNEG.H wd,ws,wt MSA Vector Bit Negate
BNEG.W wd,ws,wt MSA Vector Bit Negate
BNEG.D wd,ws,wt MSA Vector Bit Negate
BNEGI.B wd,ws,m MSA Immediate Bit Negate
BNEGI.H wd,ws,m MSA Immediate Bit Negate
BNEGI.W wd,ws,m MSA Immediate Bit Negate
BNEGI.D wd,ws,m MSA Immediate Bit Negate
BNZ.B wt,s16 MSA Immediate Branch If All Elements Are Not Zero
BNZ.H wt,s16 MSA Immediate Branch If All Elements Are Not Zero
BNZ.W wt,s16 MSA Immediate Branch If All Elements Are Not Zero
BNZ.D wt,s16 MSA Immediate Branch If All Elements Are Not Zero
BNZ.V wt,s16 MSA Immediate Branch If Not Zero (At Least One Element of Any Format Is Not Zero)
BSEL.V wd,ws,wt MSA Vector Bit Select
BSELI.B wd,ws,i8 MSA Immediate Bit Select
BSET.B wd,ws,wt MSA Vector Bit Set
BSET.H wd,ws,wt MSA Vector Bit Set
BSET.W wd,ws,wt MSA Vector Bit Set
BSET.D wd,ws,wt MSA Vector Bit Set
BSETI.B wd,ws,m MSA Immediate Bit Set
BSETI.H wd,ws,m MSA Immediate Bit Set
BSETI.W wd,ws,m MSA Immediate Bit Set
BSETI.D wd,ws,m MSA Immediate Bit Set
BZ.B wt,s16 MSA Immediate Branch If At Least One Element Is Zero
BZ.H wt,s16 MSA Immediate Branch If At Least One Element Is Zero
BZ.W wt,s16 MSA Immediate Branch If At Least One Element Is Zero
BZ.D wt,s16 MSA Immediate Branch If At Least One Element Is Zero
BZ.V wt,s16 MSA Immediate Branch If Zero (All Elements of Any Format Are Zero)
CEQ.B wd,ws,wt MSA Vector Compare Equal
CEQ.H wd,ws,wt MSA Vector Compare Equal
CEQ.W wd,ws,wt MSA Vector Compare Equal
CEQ.D wd,ws,wt MSA Vector Compare Equal
CEQI.B wd,ws,s5 MSA Immediate Compare Equal
CEQI.H wd,ws,s5 MSA Immediate Compare Equal
CEQI.W wd,ws,s5 MSA Immediate Compare Equal
CEQI.D wd,ws,s5 MSA Immediate Compare Equal
CFCMSA rd,cs MSA GPR Copy from MSA Control Register
CLEI_S.B wd,ws,s5 MSA Immediate Compare Signed Less Than or Equal
CLEI_S.H wd,ws,s5 MSA Immediate Compare Signed Less Than or Equal
CLEI_S.W wd,ws,s5 MSA Immediate Compare Signed Less Than or Equal
CLEI_S.D wd,ws,s5 MSA Immediate Compare Signed Less Than or Equal
CLEI_U.B wd,ws,u5 MSA Immediate Compare Unsigned Less Than or Equal
CLEI_U.H wd,ws,u5 MSA Immediate Compare Unsigned Less Than or Equal
CLEI_U.W wd,ws,u5 MSA Immediate Compare Unsigned Less Than or Equal
CLEI_U.D wd,ws,u5 MSA Immediate Compare Unsigned Less Than or Equal
CLE_S.B wd,ws,wt MSA Vector Compare Signed Less Than or Equal
CLE_S.H wd,ws,wt MSA Vector Compare Signed Less Than or Equal
CLE_S.W wd,ws,wt MSA Vector Compare Signed Less Than or Equal
CLE_S.D wd,ws,wt MSA Vector Compare Signed Less Than or Equal
CLE_U.B wd,ws,wt MSA Vector Compare Unsigned Less Than or Equal
CLE_U.H wd,ws,wt MSA Vector Compare Unsigned Less Than or Equal
CLE_U.W wd,ws,wt MSA Vector Compare Unsigned Less Than or Equal
CLE_U.D wd,ws,wt MSA Vector Compare Unsigned Less Than or Equal
CLTI_S.B wd,ws,s5 MSA Immediate Compare Signed Less Than
CLTI_S.H wd,ws,s5 MSA Immediate Compare Signed Less Than
CLTI_S.W wd,ws,s5 MSA Immediate Compare Signed Less Than
CLTI_S.D wd,ws,s5 MSA Immediate Compare Signed Less Than
CLTI_U.B wd,ws,u5 MSA Immediate Compare Unsigned Less Than
CLTI_U.H wd,ws,u5 MSA Immediate Compare Unsigned Less Than
CLTI_U.W wd,ws,u5 MSA Immediate Compare Unsigned Less Than
CLTI_U.D wd,ws,u5 MSA Immediate Compare Unsigned Less Than
CLT_S.B wd,ws,wt MSA Vector Compare Signed Less Than
CLT_S.H wd,ws,wt MSA Vector Compare Signed Less Than
CLT_S.W wd,ws,wt MSA Vector Compare Signed Less Than
CLT_S.D wd,ws,wt MSA Vector Compare Signed Less Than
CLT_U.B wd,ws,wt MSA Vector Compare Unsigned Less Than
CLT_U.H wd,ws,wt MSA Vector Compare Unsigned Less Than
CLT_U.W wd,ws,wt MSA Vector Compare Unsigned Less Than
CLT_U.D wd,ws,wt MSA Vector Compare Unsigned Less Than
COPY_S.B rd,ws[n] MSA Element Copy to GPR Signed
COPY_S.H rd,ws[n] MSA Element Copy to GPR Signed
COPY_S.W rd,ws[n] MSA Element Copy to GPR Signed
COPY_S.D rd,ws[n] MIPS64, MSA Element Copy to GPR Signed
COPY_U.B rd,ws[n] MSA Element Copy to GPR Unsigned
COPY_U.H rd,ws[n] MSA Element Copy to GPR Unsigned
COPY_U.W rd,ws[n] MIPS64, MSA Element Copy to GPR Unsigned
CTCMSA cd,rs MSA GPR Copy to MSA Control Register
DIV_S.B wd,ws,wt MSA Vector Signed Divide
DIV_S.H wd,ws,wt MSA Vector Signed Divide
DIV_S.W wd,ws,wt MSA Vector Signed Divide
DIV_S.D wd,ws,wt MSA Vector Signed Divide
DIV_U.B wd,ws,wt MSA Vector Unsigned Divide
DIV_U.H wd,ws,wt MSA Vector Unsigned Divide
DIV_U.W wd,ws,wt MSA Vector Unsigned Divide
DIV_U.D wd,ws,wt MSA Vector Unsigned Divide
DLSA rd,rs,rt,sa MSA Doubleword Left Shift Add
DOTP_S.H wd,ws,wt MSA Vector Signed Dot Product
DOTP_S.W wd,ws,wt MSA Vector Signed Dot Product
DOTP_S.D wd,ws,wt MSA Vector Signed Dot Product
DOTP_U.H wd,ws,wt MSA Vector Unsigned Dot Product
DOTP_U.W wd,ws,wt MSA Vector Unsigned Dot Product
DOTP_U.D wd,ws,wt MSA Vector Unsigned Dot Product
DPADD_S.H wd,ws,wt MSA Vector Signed Dot Product and Add
DPADD_S.W wd,ws,wt MSA Vector Signed Dot Product and Add
DPADD_S.D wd,ws,wt MSA Vector Signed Dot Product and Add
DPADD_U.H wd,ws,wt MSA Vector Unsigned Dot Product and Add
DPADD_U.W wd,ws,wt MSA Vector Unsigned Dot Product and Add
DPADD_U.D wd,ws,wt MSA Vector Unsigned Dot Product and Add
DPSUB_S.H wd,ws,wt MSA Vector Signed Dot Product and Subtract
DPSUB_S.W wd,ws,wt MSA Vector Signed Dot Product and Subtract
DPSUB_S.D wd,ws,wt MSA Vector Signed Dot Product and Subtract
DPSUB_U.H wd,ws,wt MSA Vector Unsigned Dot Product and Subtract
DPSUB_U.W wd,ws,wt MSA Vector Unsigned Dot Product and Subtract
DPSUB_U.D wd,ws,wt MSA Vector Unsigned Dot Product and Subtract
FADD.W wd,ws,wt MSA Vector Floating-Point Addition
FADD.D wd,ws,wt MSA Vector Floating-Point Addition
FCAF.W wd,ws,wt MSA Vector Floating-Point Quiet Compare Always False
FCAF.D wd,ws,wt MSA Vector Floating-Point Quiet Compare Always False
FCEQ.W wd,ws,wt MSA Vector Floating-Point Quiet Compare Equal
FCEQ.D wd,ws,wt MSA Vector Floating-Point Quiet Compare Equal
FCLASS.W wd,ws MSA Vector Floating-Point Class Mask
FCLASS.D wd,ws MSA Vector Floating-Point Class Mask
FCLE.W wd,ws,wt MSA Vector Floating-Point Quiet Compare Less or Equal
FCLE.D wd,ws,wt MSA Vector Floating-Point Quiet Compare Less or Equal
FCLT.W wd,ws,wt MSA Vector Floating-Point Quiet Compare Less Than
FCLT.D wd,ws,wt MSA Vector Floating-Point Quiet Compare Less Than
FCNE.W wd,ws,wt MSA Vector Floating-Point Quiet Compare Not Equal
FCNE.D wd,ws,wt MSA Vector Floating-Point Quiet Compare Not Equal
FCOR.W wd,ws,wt MSA Vector Floating-Point Quiet Compare Ordered
FCOR.D wd,ws,wt MSA Vector Floating-Point Quiet Compare Ordered
FCUEQ.W wd,ws,wt MSA Vector Floating-Point Quiet Compare Unordered or Equal
FCUEQ.D wd,ws,wt MSA Vector Floating-Point Quiet Compare Unordered or Equal
FCULE.W wd,ws,wt MSA Vector Floating-Point Quiet Compare Unordered or Less or Equal
FCULE.D wd,ws,wt MSA Vector Floating-Point Quiet Compare Unordered or Less or Equal
FCULT.W wd,ws,wt MSA Vector Floating-Point Quiet Compare Unordered or Less Than
FCULT.D wd,ws,wt MSA Vector Floating-Point Quiet Compare Unordered or Less Than
FCUN.W wd,ws,wt MSA Vector Floating-Point Quiet Compare Unordered
FCUN.D wd,ws,wt MSA Vector Floating-Point Quiet Compare Unordered
FCUNE.W wd,ws,wt MSA Vector Floating-Point Quiet Compare Unordered or Not Equal
FCUNE.D wd,ws,wt MSA Vector Floating-Point Quiet Compare Unordered or Not Equal
FDIV.W wd,ws,wt MSA Vector Floating-Point Division
FDIV.D wd,ws,wt MSA Vector Floating-Point Division
FEXDO.H wd,ws,wt MSA Vector Floating-Point Down-Convert Interchange Format
FEXDO.W wd,ws,wt MSA Vector Floating-Point Down-Convert Interchange Format
FEXP2.W wd,ws,wt MSA Vector Floating-Point Base 2 Exponentiation
FEXP2.D wd,ws,wt MSA Vector Floating-Point Base 2 Exponentiation
FEXUPL.W wd,ws MSA Vector Floating-Point Up-Convert Interchange Format Left
FEXUPL.D wd,ws MSA Vector Floating-Point Up-Convert Interchange Format Left
FEXUPR.W wd,ws MSA Vector Floating-Point Up-Convert Interchange Format Right
FEXUPR.D wd,ws MSA Vector Floating-Point Up-Convert Interchange Format Right
FFINT_S.W wd,ws MSA Vector Floating-Point Round and Convert from Signed Integer
FFINT_S.D wd,ws MSA Vector Floating-Point Round and Convert from Signed Integer
FFINT_U.W wd,ws MSA Vector Floating-Point Convert from Unsigned Integer
FFINT_U.D wd,ws MSA Vector Floating-Point Convert from Unsigned Integer
FFQL.W wd,ws MSA Vector Floating-Point Convert from Fixed-Point Left
FFQL.D wd,ws MSA Vector Floating-Point Convert from Fixed-Point Left
FFQR.W wd,ws MSA Vector Floating-Point Convert from Fixed-Point Right
FFQR.D wd,ws MSA Vector Floating-Point Convert from Fixed-Point Right
FILL.B wd,rs MSA Vector Fill from GPR
FILL.H wd,rs MSA Vector Fill from GPR
FILL.W wd,rs MSA Vector Fill from GPR
FILL.D wd,rs MIPS64, MSA Vector Fill from GPR
FLOG2.W wd,ws MSA Vector Floating-Point Base 2 Logarithm
FLOG2.D wd,ws MSA Vector Floating-Point Base 2 Logarithm
FMADD.W wd,ws,wt MSA Vector Floating-Point Multiply-Add
FMADD.D wd,ws,wt MSA Vector Floating-Point Multiply-Add
FMAX.W wd,ws,wt MSA Vector Floating-Point Maximum
FMAX.D wd,ws,wt MSA Vector Floating-Point Maximum
FMAX_A.W wd,ws,wt MSA Vector Floating-Point Maximum Based on Absolute Values
FMAX_A.D wd,ws,wt MSA Vector Floating-Point Maximum Based on Absolute Values
FMIN.W wd,ws,wt MSA Vector Floating-Point Minimum
FMIN.D wd,ws,wt MSA Vector Floating-Point Minimum
FMIN_A.W wd,ws,wt MSA Vector Floating-Point Minimum Based on Absolute Values
FMIN_A.D wd,ws,wt MSA Vector Floating-Point Minimum Based on Absolute Values
FMSUB.W wd,ws,wt MSA Vector Floating-Point Multiply-Sub
FMSUB.D wd,ws,wt MSA Vector Floating-Point Multiply-Sub
FMUL.W wd,ws,wt MSA Vector Floating-Point Multiplication
FMUL.D wd,ws,wt MSA Vector Floating-Point Multiplication
FRCP.W wd,ws MSA Vector Approximate Floating-Point Reciprocal
FRCP.D wd,ws MSA Vector Approximate Floating-Point Reciprocal
FRINT.W wd,ws MSA Vector Floating-Point Round to Integer
FRINT.D wd,ws MSA Vector Floating-Point Round to Integer
FRSQRT.W wd,ws MSA Vector Approximate Floating-Point Reciprocal of Square Root
FRSQRT.D wd,ws MSA Vector Approximate Floating-Point Reciprocal of Square Root
FSAF.W wd,ws,wt MSA Vector Floating-Point Signaling Compare Always False
FSAF.D wd,ws,wt MSA Vector Floating-Point Signaling Compare Always False
FSEQ.W wd,ws,wt MSA Vector Floating-Point Signaling Compare Equal
FSEQ.D wd,ws,wt MSA Vector Floating-Point Signaling Compare Equal
FSLE.W wd,ws,wt MSA Vector Floating-Point Signaling Compare Less or Equal
FSLE.D wd,ws,wt MSA Vector Floating-Point Signaling Compare Less or Equal
FSLT.W wd,ws,wt MSA Vector Floating-Point Signaling Compare Less Than
FSLT.D wd,ws,wt MSA Vector Floating-Point Signaling Compare Less Than
FSNE.W wd,ws,wt MSA Vector Floating-Point Signaling Compare Not Equal
FSNE.D wd,ws,wt MSA Vector Floating-Point Signaling Compare Not Equal
FSOR.W wd,ws,wt MSA Vector Floating-Point Signaling Compare Ordered
FSOR.D wd,ws,wt MSA Vector Floating-Point Signaling Compare Ordered
FSQRT.W wd,ws MSA Vector Floating-Point Square Root
FSQRT.D wd,ws MSA Vector Floating-Point Square Root
FSUB.W wd,ws,wt MSA Vector Floating-Point Subtraction
FSUB.D wd,ws,wt MSA Vector Floating-Point Subtraction
FSUEQ.W wd,ws,wt MSA Vector Floating-Point Signaling Compare Unordered or Equal
FSUEQ.D wd,ws,wt MSA Vector Floating-Point Signaling Compare Unordered or Equal
FSULE.W wd,ws,wt MSA Vector Floating-Point Signaling Compare Unordered or Less or Equal
FSULE.D wd,ws,wt MSA Vector Floating-Point Signaling Compare Unordered or Less or Equal
FSULT.W wd,ws,wt MSA Vector Floating-Point Signaling Compare Unordered or Less Than
FSULT.D wd,ws,wt MSA Vector Floating-Point Signaling Compare Unordered or Less Than
FSUN.W wd,ws,wt MSA Vector Floating-Point Signaling Compare Unordered
FSUN.D wd,ws,wt MSA Vector Floating-Point Signaling Compare Unordered
FSUNE.W wd,ws,wt MSA Vector Floating-Point Signaling Compare Unordered or Not Equal
FSUNE.D wd,ws,wt MSA Vector Floating-Point Signaling Compare Unordered or Not Equal
FTINT_S.W wd,ws MSA Vector Floating-Point Convert to Signed Integer
FTINT_S.D wd,ws MSA Vector Floating-Point Convert to Signed Integer
FTINT_U.W wd,ws MSA Vector Floating-Point Round and Convert to Unsigned Integer
FTINT_U.D wd,ws MSA Vector Floating-Point Round and Convert to Unsigned Integer
FTQ.H wd,ws,wt MSA Vector Floating-Point Convert to Fixed-Point
FTQ.W wd,ws,wt MSA Vector Floating-Point Convert to Fixed-Point
FTRUNC_S.W wd,ws MSA Vector Floating-Point Truncate and Convert to Signed Integer
FTRUNC_S.D wd,ws MSA Vector Floating-Point Truncate and Convert to Signed Integer
FTRUNC_U.W wd,ws MSA Vector Floating-Point Truncate and Convert to Unsigned Integer
FTRUNC_U.D wd,ws MSA Vector Floating-Point Truncate and Convert to Unsigned Integer
HADD_S.H wd,ws,wt MSA Vector Signed Horizontal Add
HADD_S.W wd,ws,wt MSA Vector Signed Horizontal Add
HADD_S.D wd,ws,wt MSA Vector Signed Horizontal Add
HADD_U.H wd,ws,wt MSA Vector Unsigned Horizontal Add
HADD_U.W wd,ws,wt MSA Vector Unsigned Horizontal Add
HADD_U.D wd,ws,wt MSA Vector Unsigned Horizontal Add
HSUB_S.H wd,ws,wt MSA Vector Signed Horizontal Subtract
HSUB_S.W wd,ws,wt MSA Vector Signed Horizontal Subtract
HSUB_S.D wd,ws,wt MSA Vector Signed Horizontal Subtract
HSUB_U.H wd,ws,wt MSA Vector Unsigned Horizontal Subtract
HSUB_U.W wd,ws,wt MSA Vector Unsigned Horizontal Subtract
HSUB_U.D wd,ws,wt MSA Vector Unsigned Horizontal Subtract
ILVEV.B wd,ws,wt MSA Vector Interleave Even
ILVEV.H wd,ws,wt MSA Vector Interleave Even
ILVEV.W wd,ws,wt MSA Vector Interleave Even
ILVEV.D wd,ws,wt MSA Vector Interleave Even
ILVL.B wd,ws,wt MSA Vector Interleave Left
ILVL.H wd,ws,wt MSA Vector Interleave Left
ILVL.W wd,ws,wt MSA Vector Interleave Left
ILVL.D wd,ws,wt MSA Vector Interleave Left
ILVOD.B wd,ws,wt MSA Vector Interleave Odd
ILVOD.H wd,ws,wt MSA Vector Interleave Odd
ILVOD.W wd,ws,wt MSA Vector Interleave Odd
ILVOD.D wd,ws,wt MSA Vector Interleave Odd
ILVR.B wd,ws,wt MSA Vector Interleave Right
ILVR.H wd,ws,wt MSA Vector Interleave Right
ILVR.W wd,ws,wt MSA Vector Interleave Right
ILVR.D wd,ws,wt MSA Vector Interleave Right
INSERT.B wd[n],rs MSA GPR Insert Element
INSERT.H wd[n],rs MSA GPR Insert Element
INSERT.W wd[n],rs MSA GPR Insert Element
INSERT.D wd[n],rs MIPS64, MSA GPR Insert Element
INSVE.B wd[n],ws[0] MSA Element Insert Element
INSVE.H wd[n],ws[0] MSA Element Insert Element
INSVE.W wd[n],ws[0] MSA Element Insert Element
INSVE.D wd[n],ws[0] MSA Element Insert Element
LD.B wd,s10(rs) MSA Vector Load
LD.H wd,s10(rs) MSA Vector Load
LD.W wd,s10(rs) MSA Vector Load
LD.D wd,s10(rs) MSA Vector Load
LDI.B wd,s10 MSA Immediate Load
LDI.H wd,s10 MSA Immediate Load
LDI.W wd,s10 MSA Immediate Load
LDI.D wd,s10 MSA Immediate Load
LSA rd,rs,rt,sa MSA Left Shift Add
MADDR_Q.H wd,ws,wt MSA Vector Fixed-Point Multiply and Add Rounded
MADDR_Q.W wd,ws,wt MSA Vector Fixed-Point Multiply and Add Rounded
MADDV.B wd,ws,wt MSA Vector Multiply and Add
MADDV.H wd,ws,wt MSA Vector Multiply and Add
MADDV.W wd,ws,wt MSA Vector Multiply and Add
MADDV.D wd,ws,wt MSA Vector Multiply and Add
MADD_Q.H wd,ws,wt MSA Vector Fixed-Point Multiply and Add
MADD_Q.W wd,ws,wt MSA Vector Fixed-Point Multiply and Add
MAXI_S.B wd,ws,s5 MSA Immediate Signed Maximum
MAXI_S.H wd,ws,s5 MSA Immediate Signed Maximum
MAXI_S.W wd,ws,s5 MSA Immediate Signed Maximum
MAXI_S.D wd,ws,s5 MSA Immediate Signed Maximum
MAXI_U.B wd,ws,u5 MSA Immediate Unsigned Maximum
MAXI_U.H wd,ws,u5 MSA Immediate Unsigned Maximum
MAXI_U.W wd,ws,u5 MSA Immediate Unsigned Maximum
MAXI_U.D wd,ws,u5 MSA Immediate Unsigned Maximum
MAX_A.B wd,ws,wt MSA Vector Maximum Based on Absolute Values
MAX_A.H wd,ws,wt MSA Vector Maximum Based on Absolute Values
MAX_A.W wd,ws,wt MSA Vector Maximum Based on Absolute Values
MAX_A.D wd,ws,wt MSA Vector Maximum Based on Absolute Values
MAX_S.B wd,ws,wt MSA Vector Signed Maximum
MAX_S.H wd,ws,wt MSA Vector Signed Maximum
MAX_S.W wd,ws,wt MSA Vector Signed Maximum
MAX_S.D wd,ws,wt MSA Vector Signed Maximum
MAX_U.B wd,ws,wt MSA Vector Unsigned Maximum
MAX_U.H wd,ws,wt MSA Vector Unsigned Maximum
MAX_U.W wd,ws,wt MSA Vector Unsigned Maximum
MAX_U.D wd,ws,wt MSA Vector Unsigned Maximum
MINI_S.B wd,ws,s5 MSA Immediate Signed Minimum
MINI_S.H wd,ws,s5 MSA Immediate Signed Minimum
MINI_S.W wd,ws,s5 MSA Immediate Signed Minimum
MINI_S.D wd,ws,s5 MSA Immediate Signed Minimum
MINI_U.B wd,ws,u5 MSA Immediate Unsigned Minimum
MINI_U.H wd,ws,u5 MSA Immediate Unsigned Minimum
MINI_U.W wd,ws,u5 MSA Immediate Unsigned Minimum
MINI_U.D wd,ws,u5 MSA Immediate Unsigned Minimum
MIN_A.B wd,ws,wt MSA Vector Minimum Based on Absolute Value
MIN_A.H wd,ws,wt MSA Vector Minimum Based on Absolute Value
MIN_A.W wd,ws,wt MSA Vector Minimum Based on Absolute Value
MIN_A.D wd,ws,wt MSA Vector Minimum Based on Absolute Value
MIN_S.B wd,ws,wt MSA Vector Signed Minimum
MIN_S.H wd,ws,wt MSA Vector Signed Minimum
MIN_S.W wd,ws,wt MSA Vector Signed Minimum
MIN_S.D wd,ws,wt MSA Vector Signed Minimum
MIN_U.B wd,ws,wt MSA Vector Unsigned Minimum
MIN_U.H wd,ws,wt MSA Vector Unsigned Minimum
MIN_U.W wd,ws,wt MSA Vector Unsigned Minimum
MIN_U.D wd,ws,wt MSA Vector Unsigned Minimum
MOD_S.B wd,ws,wt MSA Vector Signed Modulo
MOD_S.H wd,ws,wt MSA Vector Signed Modulo
MOD_S.W wd,ws,wt MSA Vector Signed Modulo
MOD_S.D wd,ws,wt MSA Vector Signed Modulo
MOD_U.B wd,ws,wt MSA Vector Unsigned Modulo
MOD_U.H wd,ws,wt MSA Vector Unsigned Modulo
MOD_U.W wd,ws,wt MSA Vector Unsigned Modulo
MOD_U.D wd,ws,wt MSA Vector Unsigned Modulo
MOVE.V wd,ws MSA Vector Move
MSUBR_Q.H wd,ws,wt MSA Vector Fixed-Point Multiply and Subtract Rounded
MSUBR_Q.W wd,ws,wt MSA Vector Fixed-Point Multiply and Subtract Rounded
MSUBV.B wd,ws,wt MSA Vector Multiply and Subtract
MSUBV.H wd,ws,wt MSA Vector Multiply and Subtract
MSUBV.W wd,ws,wt MSA Vector Multiply and Subtract
MSUBV.D wd,ws,wt MSA Vector Multiply and Subtract
MSUB_Q.H wd,ws,wt MSA Vector Fixed-Point Multiply and Subtract
MSUB_Q.W wd,ws,wt MSA Vector Fixed-Point Multiply and Subtract
MULR_Q.H wd,ws,wt MSA Vector Fixed-Point Multiply Rounded
MULR_Q.W wd,ws,wt MSA Vector Fixed-Point Multiply Rounded
MULV.B wd,ws,wt MSA Vector Multiply
MULV.H wd,ws,wt MSA Vector Multiply
MULV.W wd,ws,wt MSA Vector Multiply
MULV.D wd,ws,wt MSA Vector Multiply
MUL_Q.H wd,ws,wt MSA Vector Fixed-Point Multiply
MUL_Q.W wd,ws,wt MSA Vector Fixed-Point Multiply
NLOC.B wd,ws MSA Vector Leading Ones Count
NLOC.H wd,ws MSA Vector Leading Ones Count
NLOC.W wd,ws MSA Vector Leading Ones Count
NLOC.D wd,ws MSA Vector Leading Ones Count
NLZC.B wd,ws MSA Vector Leading Zeros Count
NLZC.H wd,ws MSA Vector Leading Zeros Count
NLZC.W wd,ws MSA Vector Leading Zeros Count
NLZC.D wd,ws MSA Vector Leading Zeros Count
NOR.V wd,ws,wt MSA Vector Logical Negated Or
NORI.B wd,ws,i8 MSA Immediate Logical Negated Or
OR.V wd,ws,wt MSA Vector Logical Or
ORI.B wd,ws,i8 MSA Immediate Logical Or
PCKEV.B wd,ws,wt MSA Vector Pack Even
PCKEV.H wd,ws,wt MSA Vector Pack Even
PCKEV.W wd,ws,wt MSA Vector Pack Even
PCKEV.D wd,ws,wt MSA Vector Pack Even
PCKOD.B wd,ws,wt MSA Vector Pack Odd
PCKOD.H wd,ws,wt MSA Vector Pack Odd
PCKOD.W wd,ws,wt MSA Vector Pack Odd
PCKOD.D wd,ws,wt MSA Vector Pack Odd
PCNT.B wd,ws MSA Vector Population Count
PCNT.H wd,ws MSA Vector Population Count
PCNT.W wd,ws MSA Vector Population Count
PCNT.D wd,ws MSA Vector Population Count
SAT_S.B wd,ws,m MSA Immediate Signed Saturate
SAT_S.H wd,ws,m MSA Immediate Signed Saturate
SAT_S.W wd,ws,m MSA Immediate Signed Saturate
SAT_S.D wd,ws,m MSA Immediate Signed Saturate
SAT_U.B wd,ws,m MSA Immediate Unsigned Saturate
SAT_U.H wd,ws,m MSA Immediate Unsigned Saturate
SAT_U.W wd,ws,m MSA Immediate Unsigned Saturate
SAT_U.D wd,ws,m MSA Immediate Unsigned Saturate
SHF.B wd,ws,i8 MSA Immediate Set Shuffle Elements
SHF.H wd,ws,i8 MSA Immediate Set Shuffle Elements
SHF.W wd,ws,i8 MSA Immediate Set Shuffle Elements
SLD.B wd,ws[rt] MSA GPR Columns Slide
SLD.H wd,ws[rt] MSA GPR Columns Slide
SLD.W wd,ws[rt] MSA GPR Columns Slide
SLD.D wd,ws[rt] MSA GPR Columns Slide
SLDI.B wd,ws[n] MSA Immediate Columns Slide
SLDI.H wd,ws[n] MSA Immediate Columns Slide
SLDI.W wd,ws[n] MSA Immediate Columns Slide
SLDI.D wd,ws[n] MSA Immediate Columns Slide
SLL.B wd,ws,wt MSA Vector Shift Left
SLL.H wd,ws,wt MSA Vector Shift Left
SLL.W wd,ws,wt MSA Vector Shift Left
SLL.D wd,ws,wt MSA Vector Shift Left
SLLI.B wd,ws,m MSA Immediate Shift Left
SLLI.H wd,ws,m MSA Immediate Shift Left
SLLI.W wd,ws,m MSA Immediate Shift Left
SLLI.D wd,ws,m MSA Immediate Shift Left
SPLAT.B wd,ws[rt] MSA GPR Element Splat
SPLAT.H wd,ws[rt] MSA GPR Element Splat
SPLAT.W wd,ws[rt] MSA GPR Element Splat
SPLAT.D wd,ws[rt] MSA GPR Element Splat
SPLATI.B wd,ws[n] MSA Immediate Element Splat
SPLATI.H wd,ws[n] MSA Immediate Element Splat
SPLATI.W wd,ws[n] MSA Immediate Element Splat
SPLATI.D wd,ws[n] MSA Immediate Element Splat
SRA.B wd,ws,wt MSA Vector Shift Right Arithmetic
SRA.H wd,ws,wt MSA Vector Shift Right Arithmetic
SRA.W wd,ws,wt MSA Vector Shift Right Arithmetic
SRA.D wd,ws,wt MSA Vector Shift Right Arithmetic
SRAI.B wd,ws,m MSA Immediate Shift Right Arithmetic
SRAI.H wd,ws,m MSA Immediate Shift Right Arithmetic
SRAI.W wd,ws,m MSA Immediate Shift Right Arithmetic
SRAI.D wd,ws,m MSA Immediate Shift Right Arithmetic
SRAR.B wd,ws,wt MSA Vector Shift Right Arithmetic Rounded
SRAR.H wd,ws,wt MSA Vector Shift Right Arithmetic Rounded
SRAR.W wd,ws,wt MSA Vector Shift Right Arithmetic Rounded
SRAR.D wd,ws,wt MSA Vector Shift Right Arithmetic Rounded
SRARI.B wd,ws,m MSA Immediate Shift Right Arithmetic Rounded
SRARI.H wd,ws,m MSA Immediate Shift Right Arithmetic Rounded
SRARI.W wd,ws,m MSA Immediate Shift Right Arithmetic Rounded
SRARI.D wd,ws,m MSA Immediate Shift Right Arithmetic Rounded
SRL.B wd,ws,wt MSA Vector Shift Right Logical
SRL.H wd,ws,wt MSA Vector Shift Right Logical
SRL.W wd,ws,wt MSA Vector Shift Right Logical
SRL.D wd,ws,wt MSA Vector Shift Right Logical
SRLI.B wd,ws,m MSA Immediate Shift Right Logical
SRLI.H wd,ws,m MSA Immediate Shift Right Logical
SRLI.W wd,ws,m MSA Immediate Shift Right Logical
SRLI.D wd,ws,m MSA Immediate Shift Right Logical
SRLR.B wd,ws,wt MSA Vector Shift Right Logical Rounded
SRLR.H wd,ws,wt MSA Vector Shift Right Logical Rounded
SRLR.W wd,ws,wt MSA Vector Shift Right Logical Rounded
SRLR.D wd,ws,wt MSA Vector Shift Right Logical Rounded
SRLRI.B wd,ws,m MSA Immediate Shift Right Logical Rounded
SRLRI.H wd,ws,m MSA Immediate Shift Right Logical Rounded
SRLRI.W wd,ws,m MSA Immediate Shift Right Logical Rounded
SRLRI.D wd,ws,m MSA Immediate Shift Right Logical Rounded
ST.B wd,s10(rs) MSA Vector Store
ST.H wd,s10(rs) MSA Vector Store
ST.W wd,s10(rs) MSA Vector Store
ST.D wd,s10(rs) MSA Vector Store
SUBSUS_U.B wd,ws,wt MSA Vector Unsigned Saturated Subtract of Signed from Unsigned
SUBSUS_U.H wd,ws,wt MSA Vector Unsigned Saturated Subtract of Signed from Unsigned
SUBSUS_U.W wd,ws,wt MSA Vector Unsigned Saturated Subtract of Signed from Unsigned
SUBSUS_U.D wd,ws,wt MSA Vector Unsigned Saturated Subtract of Signed from Unsigned
SUBSUU_S.B wd,ws,wt MSA Vector Signed Saturated Subtract of Unsigned Values
SUBSUU_S.H wd,ws,wt MSA Vector Signed Saturated Subtract of Unsigned Values
SUBSUU_S.W wd,ws,wt MSA Vector Signed Saturated Subtract of Unsigned Values
SUBSUU_S.D wd,ws,wt MSA Vector Signed Saturated Subtract of Unsigned Values
SUBS_S.B wd,ws,wt MSA Vector Signed Saturated Subtract of Signed Values
SUBS_S.H wd,ws,wt MSA Vector Signed Saturated Subtract of Signed Values
SUBS_S.W wd,ws,wt MSA Vector Signed Saturated Subtract of Signed Values
SUBS_S.D wd,ws,wt MSA Vector Signed Saturated Subtract of Signed Values
SUBS_U.B wd,ws,wt MSA Vector Unsigned Saturated Subtract of Unsigned Values
SUBS_U.H wd,ws,wt MSA Vector Unsigned Saturated Subtract of Unsigned Values
SUBS_U.W wd,ws,wt MSA Vector Unsigned Saturated Subtract of Unsigned Values
SUBS_U.D wd,ws,wt MSA Vector Unsigned Saturated Subtract of Unsigned Values
SUBV.B wd,ws,wt MSA Vector Subtract
SUBV.H wd,ws,wt MSA Vector Subtract
SUBV.W wd,ws,wt MSA Vector Subtract
SUBV.D wd,ws,wt MSA Vector Subtract
SUBVI.B wd,ws,u5 MSA Immediate Subtract
SUBVI.H wd,ws,u5 MSA Immediate Subtract
SUBVI.W wd,ws,u5 MSA Immediate Subtract
SUBVI.D wd,ws,u5 MSA Immediate Subtract
VSHF.B wd,ws,wt MSA Vector Data Preserving Shuffle
VSHF.H wd,ws,wt MSA Vector Data Preserving Shuffle
VSHF.W wd,ws,wt MSA Vector Data Preserving Shuffle
VSHF.D wd,ws,wt MSA Vector Data Preserving Shuffle
XOR.V wd,ws,wt MSA Vector Logical Exclusive Or
XORI.B wd,ws,i8 MSA Immediate Logical Exclusive Or

MIPS ASE-MT ISA Reference

MD00378-2B-MIPS32MT-AFP-01.12

DMT rt MIPS MT Disable Multi-Threaded Execution
DVPE rt MIPS MT Disable Virtual Processor Execution
EMT rt MIPS MT Enable Multi-Threaded Execution
EVPE rt MIPS MT Enable Virtual Processor Execution
FORK rd, rs, rt MIPS MT Allocate and Schedule a New Thread
MFTR rd, rt, u, sel, h MIPS MT Move from Thread Context
MTTR rt, rd, u, sel, h MIPS MT Move to Thread Context
YIELD rd, rs MIPS MT Conditionally Deschedule or Deallocate the Current Thread

MIPS ASE-SMART ISA Reference

MD00101-2B-SMARTMIPS32-AFP-03.00

LWXS rd, index(base) SmartMIPS Crypto Load Word Indexed, Scaled
MADDP rs, rt SmartMIPS Crypto Multiply and Add Polynomial Basis Word to Hi,Lo
MADDU rs, rt SmartMIPS Crypto Multiply and Add Unsigned Word to Hi,Lo
MFLHXU rd SmartMIPS Crypto Move from Extended Carry, Hi and Lo (Unsigned)
MTLHX rs SmartMIPS Crypto Move to Lo, Hi, and Extended Carry
MULTP rs, rt SmartMIPS Crypto Multiply Binary Polynomial Basis Word
MULTU rs, rt SmartMIPS Crypto Multiply Unsigned Word
PPERM rs, rt SmartMIPS Crypto Partial Permutation of Word Data into ACX-Hi-Lo Accumulator
ROTR rd, rt, sa SmartMIPS Crypto Rotate Word Right
ROTRV rd, rt, rs SmartMIPS Crypto Rotate Word Right Variable

MIPS ASE-VZ ISA Reference

MD00847-2B-VZMIPS64-AFP-01.06

DMFGC0 rt, rd, sel MIPS64 Doubleword Move from Guest Coprocessor 0
DMTGC0 rt, rd, sel MIPS64 Doubleword Move to Guest Coprocessor 0
MFGC0 rt, rd, sel MIPS32 Move from Guest Coprocessor 0
MFHGC0 rt, rd, sel MIPS32 Release 5 Move from High Guest Coprocessor 0
MTGC0 rt, rd, sel MIPS32 Move to Guest Coprocessor 0
MTHGC0 rt, rd, sel MIPS32 Release 5 Move to High Guest Coprocessor 0
TLBGINV MIPS32 Guest TLB Invalidate
TLBGINVF MIPS32 Guest TLB Invalidate Flush
TLBGP MIPS32 Probe Guest TLB for Matching Entry
TLBGR MIPS32 Read Indexed Guest TLB Entry
TLBGWI MIPS32 Write Indexed Guest TLB Entry
TLBGWR MIPS32 Write Random Guest TLB Entry
TLBINV MIPS32 TLB Invalidate
TLBINVF MIPS32 TLB Invalidate Flush
TLBP MIPS32 Probe TLB for Matching Entry
TLBR MIPS32 Read Indexed TLB Entry
TLBWI MIPS32 Write Indexed TLB Entry
TLBWR MIPS32 Write Random TLB Entry