Encoding:

COP1X

010011

base

index

fs

0

00000

SUXC1

001101

6

5

5

5

5

6

Format: 

SUXC1 fs, index(base)

MIPS64, MIPS32 Release 2, removed in Release 6

Store Doubleword Indexed Unaligned from Floating Point

Purpose:

Store Doubleword Indexed Unaligned from Floating Point

To store a doubleword from an FPR to memory (GPR+GPR addressing) ignoring alignment.

Description: 

 memory[(GPR[base] + GPR[index])PSIZE-1..3] = FPR[fs]

The contents of the 64-bit doubleword in FPR fs is stored at the memory location specified by the effective address.

The contents of GPR index and GPR base are added to form the effective address. The effective address is doubleword-aligned; EffectiveAddress2..0 are ignored.

Restrictions:

The result of this instruction is UNPREDICTABLE if the processor is executing in the FR=0 32-bit FPU register model. The instruction is predictable if executing on a 64-bit FPU in the FR=1 mode, but not with FR=0, and not on a 32-bit FPU.

Availability and Compatibility

This instruction has been removed in Release 6.

Operation: 

vAddr = (GPR[base]+GPR[index])63..3  || 03
(pAddr, CCA) = AddressTranslation(vAddr, DATA, STORE)
datadoubleword = ValueFPR(fs, UNINTERPRETED_DOUBLEWORD)
StoreMemory(CCA, DOUBLEWORD, datadoubleword, pAddr, vAddr, DATA)
paddr = paddr xor ((BigEndianCPU xor ReverseEndian) || 02)
StoreMemory(CCA, WORD, datadoubleword31..0, pAddr, vAddr, DATA)
paddr = paddr xor 0b100
StoreMemory(CCA, WORD, datadoubleword63..32, pAddr, vAddr+4, DATA)

Exceptions:

Coprocessor Unusable, Reserved Instruction, TLB Refill, TLB Invalid, TLB Modified, Watch